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Searched refs:UZP2 (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedKryoDetails.td2329 (instregex "((TRN1|TRN2|ZIP1|UZP1|UZP2)v2i64|ZIP2(v2i64|v4i32|v8i16|v16i8))")>;
2359 (instregex "(UZP1|UZP2)(v4i32|v8i16|v16i8)")>;
2365 (instregex "(UZP1|UZP2|ZIP1|ZIP2)(v2i32|v4i16|v8i8)")>;
H A DAArch64ISelLowering.h214 UZP2, enumerator
H A DAArch64SchedFalkorDetails.td920 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(TRN1|TRN2|ZIP1|UZP1|UZP2|ZIP2|XTN)(v2i32|v2i64|v4i16|v4i32|v8i8|v8i16|v16i8)$")>;
H A DAArch64ISelLowering.cpp2637 MAKE_CASE(AArch64ISD::UZP2) in getTargetNodeName()
5774 return DAG.getNode(AArch64ISD::UZP2, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
12833 return DAG.getNode(AArch64ISD::UZP2, dl, VT, OpLHS, OpRHS); in GeneratePerfectShuffle()
13238 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; in LowerVECTOR_SHUFFLE()
13251 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; in LowerVECTOR_SHUFFLE()
14134 return DAG.getNode(AArch64ISD::UZP2, dl, VT, LHS, RHS); in LowerBUILD_VECTOR()
22173 if (N->getOpcode() == AArch64ISD::UZP2) in performUzpCombine()
25373 case AArch64ISD::UZP2: in PerformDAGCombine()
27945 SDValue Odd = DAG.getNode(AArch64ISD::UZP2, DL, OpVT, Op.getOperand(0), in LowerVECTOR_DEINTERLEAVE()
28309 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; in LowerFixedLengthVECTOR_SHUFFLEToSVE()
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H A DAArch64SchedThunderX3T110.td1643 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
H A DAArch64SchedA64FX.td1695 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
H A DAArch64InstrInfo.td747 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
6408 // Prioritize ADDHN and SUBHN over UZP2.
6515 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;