Home
last modified time | relevance | path

Searched refs:UZP1 (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SelectionDAGInfo.cpp78 case AArch64ISD::UZP1: in verifyTargetNode()
H A DAArch64ISelLowering.cpp6075 return DAG.getNode(AArch64ISD::UZP1, DL, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
13700 return DAG.getNode(AArch64ISD::UZP1, DL, VT, OpLHS, OpRHS); in GeneratePerfectShuffle()
14071 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; in LowerVECTOR_SHUFFLE()
14084 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; in LowerVECTOR_SHUFFLE()
15026 return DAG.getNode(AArch64ISD::UZP1, DL, VT, LHS, RHS); in LowerBUILD_VECTOR()
15527 Narrow = DAG.getNode(AArch64ISD::UZP1, DL, NarrowVT, Vec1, HiVec0); in LowerINSERT_SUBVECTOR()
15533 Narrow = DAG.getNode(AArch64ISD::UZP1, DL, NarrowVT, LoVec0, Vec1); in LowerINSERT_SUBVECTOR()
15634 return DAG.getNode(AArch64ISD::UZP1, DL, VT, ResultLoCast, ResultHiCast); in LowerDIV()
22500 SDValue UZP = DAG.getNode(Idx < 2 ? AArch64ISD::UZP1 : AArch64ISD::UZP2, DL, in performZExtDeinterleaveShuffleCombine()
22560 if (Op.getOpcode() != AArch64ISD::UZP1 && Op.getOpcode() != AArch64ISD::UZP2) in performZExtUZPCombine()
[all …]
H A DAArch64SchedKryoDetails.td2329 (instregex "((TRN1|TRN2|ZIP1|UZP1|UZP2)v2i64|ZIP2(v2i64|v4i32|v8i16|v16i8))")>;
2359 (instregex "(UZP1|UZP2)(v4i32|v8i16|v16i8)")>;
2365 (instregex "(UZP1|UZP2|ZIP1|ZIP2)(v2i32|v4i16|v8i8)")>;
H A DAArch64SchedFalkorDetails.td920 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(TRN1|TRN2|ZIP1|UZP1|UZP2|ZIP2|XTN)(v2i32|v2i64|v4i16|v4i32|v8i8|v8i16|v16i8)$")>;
H A DAArch64SchedThunderX3T110.td1643 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
H A DAArch64SchedA64FX.td1695 (instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
H A DAArch64InstrInfo.td881 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
6954 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
6970 (!cast<Instruction>("UZP1"#ConcatTy) V128:$Vn, V128:$Vm)>;
6984 (!cast<Instruction>("XTN"#Ty) (!cast<Instruction>("UZP1"#ConcatTy) V128:$Vn, V128:$Vm))>;