| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 40 UXTB,
60 case AArch64_AM::UXTB: return "uxtb"; in getShiftExtendName()
127 case 0: return AArch64_AM::UXTB; in getExtendType()
154 case AArch64_AM::UXTB: return 0; break; in getExtendEncoding()
41 UXTB, global() enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedPredicates.td | 18 def CheckExtUXTB : CheckImmOperand_s<3, "AArch64_AM::UXTB">;
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| H A D | AArch64SchedCyclone.td | 166 // EXAMPLE: ADDXre Xn, Xm, UXTB #1
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| H A D | AArch64ExpandPseudoInsts.cpp | 1477 AArch64_AM::getArithExtendImm(AArch64_AM::UXTB, 0), in expandMI()
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| H A D | AArch64ISelDAGToDAG.cpp | 827 return AArch64_AM::UXTB; in getExtendTypeForNode()
845 return !IsLoadStore ? AArch64_AM::UXTB : AArch64_AM::InvalidShiftExtend; in getExtendTypeForNode()
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| H A D | AArch64InstrInfo.cpp | 956 case AArch64_AM::UXTB: in isFalkorShiftExtFast()
990 case AArch64_AM::UXTB: in isFalkorShiftExtFast()
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| H A D | AArch64FastISel.cpp | 1178 ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB; in emitAddSub()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 611 UXTB, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 306 STORE_OPCODE(ZEXT8, UXTB); in OpcodeCache()
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| H A D | ARMScheduleM55.td | 55 // NOPs, ITs, Brs, ADDri/SUBri, UXTB/H, SXTB/H and MOVri's. NOPs and IT's are
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| H A D | ARMScheduleR52.td | 215 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
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| H A D | ARMScheduleSwift.td | 161 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
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| H A D | ARMScheduleA57.td | 360 // Sign/zero extend, normal: SXTB, SXTH, UXTB, UXTH
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| H A D | ARMFastISel.cpp | 2909 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
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| H A D | ARMInstrThumb.td | 1791 // restrict the register class for the UXTB/UXTH ops used in the expansion.
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| H A D | ARMInstrInfo.td | 3784 def UXTB : AI_ext_rrot<0b01101110,
6161 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
6302 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
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| H A D | ARMExpandPseudoInsts.cpp | 3162 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, ARM::UXTB, in ExpandMI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1537 return (ET == AArch64_AM::UXTB || ET == AArch64_AM::SXTB || in isExtend()
1550 return ET == AArch64_AM::UXTB || ET == AArch64_AM::SXTB || in isExtend64()
3596 .Case("uxtb", AArch64_AM::UXTB) in tryParseOptionalShiftExtend()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 7614 return IsLoadStore ? AArch64_AM::InvalidShiftExtend : AArch64_AM::UXTB; in getExtendTypeForInst()
7637 return !IsLoadStore ? AArch64_AM::UXTB : AArch64_AM::InvalidShiftExtend; in getExtendTypeForInst()
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