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Searched refs:UREM (Results 1 – 25 of 46) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiTargetTransformInfo.h108 case ISD::UREM:
H A DLanaiISelLowering.cpp111 setOperationAction(ISD::UREM, MVT::i32, Expand); in LanaiTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1364 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1368 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1372 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1376 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1381 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1385 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1389 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1393 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
2105 case ISD::UREM: in maybeLoweredToCall()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h252 UREM, enumerator
H A DSDPatternMatch.h603 return BinaryOpc_match<LHS, RHS, false>(ISD::UREM, L, R);
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp364 if ((ISD == ISD::UDIV || ISD == ISD::UREM) && in getArithmeticInstrCost()
444 { ISD::UREM, MVT::v16i32, { 7 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
485 { ISD::UREM, MVT::v8i32, { 7 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
526 { ISD::UREM, MVT::v8i32, { 16 } }, // 2*pmuludq+mul+sub sequence + split. in getArithmeticInstrCost()
557 { ISD::UREM, MVT::v4i32, { 7 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
572 { ISD::UREM, MVT::v64i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
577 { ISD::UREM, MVT::v32i16, { 8 } }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
590 { ISD::UREM, MVT::v64i8, { 32 } }, // 4*ext+4*pmulhw+mul+sub sequence in getArithmeticInstrCost()
595 { ISD::UREM, MVT::v32i16, { 16 } }, // 2*vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
600 { ISD::UREM, MVT::v16i32, { 17 } }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1927 case ISD::UREM: in selectDivRem()
1944 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
2049 if (!selectBinaryOp(I, ISD::UREM)) in fastSelectInstruction()
2050 return selectDivRem(I, ISD::UREM); in fastSelectInstruction()
H A DMipsSEISelLowering.cpp240 setOperationAction(ISD::UREM, MVT::i32, Legal); in MipsSETargetLowering()
287 setOperationAction(ISD::UREM, MVT::i64, Legal); in MipsSETargetLowering()
345 setOperationAction(ISD::UREM, Ty, Legal); in addMSAIntType()
2058 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp351 case ISD::UREM: in LegalizeOp()
1114 case ISD::UREM: in Expand()
1830 assert((Node->getOpcode() == ISD::SREM || Node->getOpcode() == ISD::UREM) && in ExpandREM()
H A DSelectionDAGBuilder.h554 void visitURem(const User &I) { visitBinary(I, ISD::UREM); } in visitURem()
H A DSelectionDAGDumper.cpp270 case ISD::UREM: return "urem"; in getOperationName()
H A DFastISel.cpp501 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) && in selectBinaryOp()
1829 return selectBinaryOp(I, ISD::UREM); in selectOperator()
H A DTargetLowering.cpp4892 if (N0.getOpcode() == ISD::UREM && N1C->isZero() && in SimplifySetCC()
5365 if ((N0.getOpcode() == ISD::UREM || N0.getOpcode() == ISD::SREM) && in SimplifySetCC()
5370 if (N0.getOpcode() == ISD::UREM) { in SimplifySetCC()
7765 (Opcode == ISD::UREM || Opcode == ISD::UDIV || Opcode == ISD::UDIVREM) && in expandDIVREMByConstant()
7867 DAG.getNode(ISD::UREM, dl, HiLoVT, Sum, in expandDIVREMByConstant()
7871 if (Opcode != ISD::UREM) { in expandDIVREMByConstant()
8028 ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC); in expandFunnelShift()
8043 ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC); in expandFunnelShift()
8107 SDValue ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Op1, BitWidthC); in expandROT()
H A DLegalizeDAG.cpp3771 case ISD::UREM: in ExpandNode()
4954 case ISD::UREM: in ConvertNodeToLibcall()
5231 case ISD::UREM: in PromoteNode()
5257 case ISD::UREM: in PromoteNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp134 setOperationAction(ISD::UREM, MVT::i8, Promote); in MSP430TargetLowering()
140 setOperationAction(ISD::UREM, MVT::i16, LibCall); in MSP430TargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp889 case ISD::UREM: in canOpTrap()
1783 case URem: return ISD::UREM; in InstructionOpcodeToISD()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp144 setOperationAction({ISD::UDIV, ISD::UREM}, MVT::i32, Custom); in LoongArchTargetLowering()
261 setOperationAction({ISD::MUL, ISD::SDIV, ISD::SREM, ISD::UDIV, ISD::UREM}, in LoongArchTargetLowering()
308 setOperationAction({ISD::MUL, ISD::SDIV, ISD::SREM, ISD::UDIV, ISD::UREM}, in LoongArchTargetLowering()
2624 case ISD::UREM: in getLoongArchWOpcode()
2821 case ISD::UREM: in ReplaceNodeResults()
3953 return DAG.getNode(ISD::UREM, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp541 ISD::UMIN, ISD::UMULO, ISD::UMUL_LOHI, ISD::UREM, in NVPTXTargetLowering()
699 setI16x2OperationAction(ISD::UREM, MVT::v2i16, Legal, Custom); in NVPTXTargetLowering()
732 ISD::LOAD, ISD::MUL, ISD::SHL, ISD::SREM, ISD::UREM, in NVPTXTargetLowering()
2812 case ISD::UREM: in LowerOperation()
5586 assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM); in PerformREMCombine()
6027 case ISD::UREM: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def204 HELPER_REGISTER_BINARY_INT_VP(vp_urem, VP_UREM, URem, UREM)
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp153 setOperationAction(ISD::UREM, MVT::i8, Expand); in AVRTargetLowering()
154 setOperationAction(ISD::UREM, MVT::i16, Expand); in AVRTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4630 case ISD::UREM: in selectRem()
5127 if (!selectBinaryOp(I, ISD::UREM)) in fastSelectInstruction()
5128 return selectRem(I, ISD::UREM); in fastSelectInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp59 setOperationAction(ISD::UREM, MVT::i32, Expand); in CSKYTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp1737 case ISD::UREM: in getArithmeticInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1673 setOperationAction(ISD::UREM, MVT::i32, Expand); in SparcTargetLowering()
1680 setOperationAction(ISD::UREM, MVT::i64, Expand); in SparcTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1600 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, in HexagonTargetLowering()
1647 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO, in HexagonTargetLowering()

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