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Searched refs:UREM (Results 1 – 25 of 48) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiTargetTransformInfo.h109 case ISD::UREM:
H A DLanaiISelLowering.cpp109 setOperationAction(ISD::UREM, MVT::i32, Expand); in LanaiTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1389 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1393 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1397 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1401 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1406 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1410 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1414 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1418 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
2229 case ISD::UREM: in maybeLoweredToCall()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h265 UREM, enumerator
H A DSDPatternMatch.h860 return BinaryOpc_match<LHS, RHS>(ISD::UREM, L, R);
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp363 if ((ISD == ISD::UDIV || ISD == ISD::UREM) && in getArithmeticInstrCost()
443 { ISD::UREM, MVT::v16i32, { 7 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
484 { ISD::UREM, MVT::v8i32, { 7 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
525 { ISD::UREM, MVT::v8i32, { 16 } }, // 2*pmuludq+mul+sub sequence + split. in getArithmeticInstrCost()
556 { ISD::UREM, MVT::v4i32, { 7 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
571 { ISD::UREM, MVT::v64i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
576 { ISD::UREM, MVT::v32i16, { 8 } }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
589 { ISD::UREM, MVT::v64i8, { 32 } }, // 4*ext+4*pmulhw+mul+sub sequence in getArithmeticInstrCost()
594 { ISD::UREM, MVT::v32i16, { 16 } }, // 2*vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
599 { ISD::UREM, MVT::v16i32, { 17 } }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1939 case ISD::UREM: in selectDivRem()
1959 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
2064 if (!selectBinaryOp(I, ISD::UREM)) in fastSelectInstruction()
2065 return selectDivRem(I, ISD::UREM); in fastSelectInstruction()
H A DMipsSEISelLowering.cpp279 setOperationAction(ISD::UREM, MVT::i32, Legal); in MipsSETargetLowering()
326 setOperationAction(ISD::UREM, MVT::i64, Legal); in MipsSETargetLowering()
384 setOperationAction(ISD::UREM, Ty, Legal); in addMSAIntType()
2102 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.h553 void visitURem(const User &I) { visitBinary(I, ISD::UREM); } in visitURem()
H A DLegalizeVectorOps.cpp362 case ISD::UREM: in LegalizeOp()
1250 case ISD::UREM: in Expand()
2158 assert((Node->getOpcode() == ISD::SREM || Node->getOpcode() == ISD::UREM) && in ExpandREM()
H A DSelectionDAGDumper.cpp287 case ISD::UREM: return "urem"; in getOperationName()
H A DFastISel.cpp498 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) && in selectBinaryOp()
1771 return selectBinaryOp(I, ISD::UREM); in selectOperator()
H A DTargetLowering.cpp5108 if (N0.getOpcode() == ISD::UREM && N1C->isZero() && in SimplifySetCC()
5582 if ((N0.getOpcode() == ISD::UREM || N0.getOpcode() == ISD::SREM) && in SimplifySetCC()
5587 if (N0.getOpcode() == ISD::UREM) { in SimplifySetCC()
7984 (Opcode == ISD::UREM || Opcode == ISD::UDIV || Opcode == ISD::UDIVREM) && in expandDIVREMByConstant()
8086 DAG.getNode(ISD::UREM, dl, HiLoVT, Sum, in expandDIVREMByConstant()
8090 if (Opcode != ISD::UREM) { in expandDIVREMByConstant()
8246 ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC); in expandFunnelShift()
8261 ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC); in expandFunnelShift()
8325 SDValue ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Op1, BitWidthC); in expandROT()
H A DLegalizeDAG.cpp3910 case ISD::UREM: in ExpandNode()
5163 case ISD::UREM: in ConvertNodeToLibcall()
5442 case ISD::UREM: in PromoteNode()
5468 case ISD::UREM: in PromoteNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp133 setOperationAction(ISD::UREM, MVT::i8, Promote); in MSP430TargetLowering()
139 setOperationAction(ISD::UREM, MVT::i16, LibCall); in MSP430TargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp155 setOperationAction(ISD::UREM, MVT::i32, Legal); in XtensaTargetLowering()
160 setOperationAction(ISD::UREM, MVT::i32, Expand); in XtensaTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp988 case ISD::UREM: in canOpTrap()
1870 case URem: return ISD::UREM; in InstructionOpcodeToISD()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp652 ISD::UMIN, ISD::UMULO, ISD::UMUL_LOHI, ISD::UREM, in NVPTXTargetLowering()
809 setI16x2OperationAction(ISD::UREM, MVT::v2i16, Legal, Custom); in NVPTXTargetLowering()
842 ISD::MUL, ISD::SHL, ISD::SREM, ISD::UREM, ISD::VSELECT, in NVPTXTargetLowering()
2953 case ISD::UREM: in LowerOperation()
5321 assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM); in PerformREMCombine()
5805 case ISD::UREM: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def176 HELPER_REGISTER_BINARY_INT_VP(vp_urem, VP_UREM, URem, UREM)
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp152 setOperationAction(ISD::UREM, MVT::i8, Expand); in AVRTargetLowering()
153 setOperationAction(ISD::UREM, MVT::i16, Expand); in AVRTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp159 setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM}, MVT::i32, in LoongArchTargetLowering()
300 setOperationAction({ISD::MUL, ISD::SDIV, ISD::SREM, ISD::UDIV, ISD::UREM}, in LoongArchTargetLowering()
367 setOperationAction({ISD::MUL, ISD::SDIV, ISD::SREM, ISD::UDIV, ISD::UREM}, in LoongArchTargetLowering()
3793 case ISD::UREM: in getLoongArchWOpcode()
4029 case ISD::UREM: in ReplaceNodeResults()
5448 return DAG.getNode(ISD::UREM, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4633 case ISD::UREM: in selectRem()
5133 if (!selectBinaryOp(I, ISD::UREM)) in fastSelectInstruction()
5134 return selectRem(I, ISD::UREM); in fastSelectInstruction()
H A DAArch64TargetTransformInfo.cpp4080 case ISD::UREM: { in getArithmeticInstrCost()
4088 if (ISD == ISD::UREM && Op2Info.isPowerOf2()) in getArithmeticInstrCost()
4093 if (ISD == ISD::UDIV || ISD == ISD::UREM) { in getArithmeticInstrCost()
4114 return DivCost + (ISD == ISD::UREM ? MulCost + AddCost : 0); in getArithmeticInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp59 setOperationAction(ISD::UREM, MVT::i32, Expand); in CSKYTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1664 setOperationAction(ISD::UREM, MVT::i32, Expand); in SparcTargetLowering()
1671 setOperationAction(ISD::UREM, MVT::i64, Expand); in SparcTargetLowering()

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