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Searched refs:UMIN (Results 1 – 25 of 36) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3605 { ISD::UMIN, MVT::v32i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3606 { ISD::UMIN, MVT::v64i8, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3675 { ISD::UMIN, MVT::v8i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3676 { ISD::UMIN, MVT::v16i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3677 { ISD::UMIN, MVT::v32i16, { 3, 7, 5, 5 } }, in getIntrinsicInstrCost()
3678 { ISD::UMIN, MVT::v64i8, { 3, 7, 5, 5 } }, in getIntrinsicInstrCost()
3679 { ISD::UMIN, MVT::v4i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3680 { ISD::UMIN, MVT::v2i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3822 { ISD::UMIN, MVT::v2i64, { 2, 8, 5, 6 } }, in getIntrinsicInstrCost()
3823 { ISD::UMIN, MVT::v4i64, { 2, 8, 5, 8 } }, in getIntrinsicInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h698 UMIN, enumerator
H A DSDPatternMatch.h584 return BinaryOpc_match<LHS, RHS, true>(ISD::UMIN, L, R);
H A DTargetLowering.h2886 case ISD::UMIN: in isCommutativeBinOp()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp105 case ISD::UMIN: in PromoteIntegerResult()
1071 return matcher.getNode(ISD::UMIN, dl, PromotedType, Add, SatMax); in PromoteIntRes_ADDSUBSHLSAT()
1171 return DAG.getNode(ISD::UMIN, dl, VT, V, in SaturateWidenedDIVFIX()
2869 case ISD::UMIN: in ExpandIntegerResult()
3249 return std::make_pair(ISD::SETLT, ISD::UMIN); in getExpandedMinMaxOps()
3250 case ISD::UMIN: in getExpandedMinMaxOps()
3251 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
3306 if (RHSVal && (N->getOpcode() == ISD::UMIN || N->getOpcode() == ISD::UMAX) && in ExpandIntRes_MINMAX()
3358 case ISD::UMIN: in ExpandIntRes_MINMAX()
H A DSelectionDAGDumper.cpp306 case ISD::UMIN: return "umin"; in getOperationName()
H A DTargetLowering.cpp2242 case ISD::UMIN: in SimplifyDemandedBits()
2276 case ISD::UMIN: in SimplifyDemandedBits()
9219 isOperationLegal(ISD::UMIN, VT)) { in expandABS()
9222 return DAG.getNode(ISD::UMIN, dl, VT, Op, in expandABS()
9267 unsigned MinOpc = IsSigned ? ISD::SMIN : ISD::UMIN; in expandABD()
10129 return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx, Sub); in clampDynamicVectorIndex()
10137 return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx, in clampDynamicVectorIndex()
10263 if (Opcode == ISD::UMIN && isOperationLegal(ISD::SUB, VT) && in expandIntMINMAX()
10318 case ISD::UMIN: in expandIntMINMAX()
10342 if (Opcode == ISD::UADDSAT && isOperationLegal(ISD::UMIN, VT)) { in expandAddSubSat()
[all …]
H A DLegalizeVectorOps.cpp437 case ISD::UMIN: in LegalizeOp()
1021 case ISD::UMIN: in Expand()
H A DSelectionDAG.cpp465 return ISD::UMIN; in getVecReduceBaseOpcode()
4073 case ISD::UMIN: { in computeKnownBits()
4404 Val.getOpcode() == ISD::UMIN || Val.getOpcode() == ISD::UMAX) in isKnownToBeAPowerOfTwo()
4701 case ISD::UMIN: in ComputeNumSignBits()
5265 case ISD::UMIN: in canCreateUndefOrPoison()
5592 case ISD::UMIN: in isKnownNeverZero()
6268 case ISD::UMIN: return C1.ule(C2) ? C1 : C2; in FoldValue()
7027 case ISD::UMIN: in getNode()
11904 case ISD::UMIN: in isNeutralConstant()
12684 SDValue Lo = getNode(ISD::UMIN, DL, VT, N, HalfNumElts); in SplitEVL()
[all …]
H A DLegalizeDAG.cpp3615 case ISD::UMIN: in ExpandNode()
3624 case ISD::UMIN: Pred = ISD::SETULT; break; in ExpandNode()
5234 case ISD::UMIN: in PromoteNode()
5260 case ISD::UMIN: in PromoteNode()
H A DDAGCombiner.cpp1880 case ISD::UMIN: in visit()
3730 RHS = DAG.getNode(ISD::UMIN, DL, SrcVT, RHS, SatLimit); in getTruncatedUSUBSAT()
3758 if (Op1.getOpcode() == ISD::UMIN && Op1.hasOneUse()) { in foldSubToUSubSat()
3769 Op1.getOperand(0).getOpcode() == ISD::UMIN && in foldSubToUSubSat()
5709 bool IsSatBroken = Opcode == ISD::UMIN && N0.getOpcode() == ISD::SMAX; in visitIMINMAX()
5714 case ISD::SMIN: AltOpcode = ISD::UMIN; break; in visitIMINMAX()
5716 case ISD::UMIN: AltOpcode = ISD::SMIN; break; in visitIMINMAX()
5728 if (Opcode == ISD::UMIN) in visitIMINMAX()
5739 case ISD::UMIN: in visitIMINMAX()
6053 SDValue Min = DAG.getNode(ISD::UMIN, DL, OpVT, LR, RR); in foldLogicOfSetCCs()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA64FX.td2138 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_B")>;
2146 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_H")>;
2154 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_S")>;
2162 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_D")>;
H A DAArch64ISelLowering.cpp669 setOperationAction(ISD::UMIN, MVT::i32, Legal); in AArch64TargetLowering()
670 setOperationAction(ISD::UMIN, MVT::i64, Legal); in AArch64TargetLowering()
1260 setOperationAction(ISD::UMIN, VT, Custom); in AArch64TargetLowering()
1452 setOperationAction(ISD::UMIN, VT, Custom); in AArch64TargetLowering()
1724 setOperationAction(ISD::UMIN, MVT::v1i64, Custom); in AArch64TargetLowering()
1725 setOperationAction(ISD::UMIN, MVT::v2i64, Custom); in AArch64TargetLowering()
1904 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
2105 setOperationAction(ISD::UMIN, VT, Default); in addTypeForFixedLengthSVE()
4559 Sat = DAG.getNode(ISD::UMIN, DL, IntVT, NativeCvt, MinC); in LowerVectorFP_TO_INT_SAT()
4616 Sat = DAG.getNode(ISD::UMIN, DL, DstVT, NativeCvt, MinC); in LowerFP_TO_INT_SAT()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp493 setOperationAction({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX}, MVT::i32, in AMDGPUTargetLowering()
3173 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, NewOpr, ConstVal); in LowerCTLZ_CTTZ()
3197 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, OprLo, OprHi); in LowerCTLZ_CTTZ()
3200 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, NewOpr, Const64); in LowerCTLZ_CTTZ()
3275 ShAmt = DAG.getNode(ISD::UMIN, SL, MVT::i32, ShAmt, MaxShAmt); in LowerINT_TO_FP32()
3297 SDValue Adjust = DAG.getNode(ISD::UMIN, SL, MVT::i32, in LowerINT_TO_FP32()
H A DSIISelLowering.cpp552 setOperationAction({ISD::Constant, ISD::SMIN, ISD::SMAX, ISD::UMIN, in SITargetLowering()
775 ISD::SRA, ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX, in SITargetLowering()
794 ISD::MUL, ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, in SITargetLowering()
908 ISD::UMIN, in SITargetLowering()
4153 DAG.getNode(ISD::UMIN, SL, MVT::i32, NewMode, OffsetEnum); in lowerSET_ROUNDING()
5850 case ISD::UMIN: in LowerOperation()
13039 case ISD::UMIN: in minMaxOpcToMin3Max3Opc()
13165 case ISD::UMIN: in supportsMin3Max3()
13226 if (Opc == ISD::UMIN && Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) { in performMinMaxCombine()
13231 if (Opc == ISD::UMAX && Op0.getOpcode() == ISD::UMIN && Op0.hasOneUse()) { in performMinMaxCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def228 VP_PROPERTY_FUNCTIONAL_SDOPC(UMIN)
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp471 case ISD::UMIN: in NVPTXTargetLowering()
541 ISD::UMIN, ISD::UMULO, ISD::UMUL_LOHI, ISD::UREM, in NVPTXTargetLowering()
679 setOperationAction(ISD::UMIN, Ty, Legal); in NVPTXTargetLowering()
689 setI16x2OperationAction(ISD::UMIN, MVT::v2i16, Legal, Custom); in NVPTXTargetLowering()
2805 case ISD::UMIN: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td636 (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND|MIN|MAX|UMIN|UMAX)"
H A DMipsSEISelLowering.cpp347 setOperationAction(ISD::UMIN, Ty, Legal); in addMSAIntType()
2034 return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2046 return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
H A DMipsScheduleGeneric.td1621 (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND|MIN|MAX|UMIN|UMAX)"
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp378 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, XLenVT, in RISCVTargetLowering()
381 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, MVT::i32, in RISCVTargetLowering()
829 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, VT, in RISCVTargetLowering()
1240 {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX, ISD::ABS}, VT, Custom); in RISCVTargetLowering()
1456 setOperationAction(ISD::UMIN, XLenVT, Legal); in RISCVTargetLowering()
1480 setTargetDAGCombine({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}); in RISCVTargetLowering()
5512 Res = DAG.getNode(ISD::UMIN, DL, VT, Res, DAG.getConstant(EltSize, DL, VT)); in lowerCTLZ_CTTZ_ZERO_UNDEF()
5992 OP_CASE(UMIN) in getRISCVVLOp()
6015 VP_CASE(UMIN) // VP_UMIN in getRISCVVLOp()
7033 case ISD::UMIN in LowerOperation()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp216 setOperationAction(ISD::UMIN, T, Legal); in initializeHVXLowering()
321 setOperationAction(ISD::UMIN, T, Custom); in initializeHVXLowering()
3183 case ISD::UMIN: in LowerHvxOperation()
H A DHexagonISelLowering.cpp1560 {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) { in HexagonTargetLowering()
1734 setOperationAction(ISD::UMIN, VT, Legal); in HexagonTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp259 setOperationAction({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}, VT, in LoongArchTargetLowering()
306 setOperationAction({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}, VT, in LoongArchTargetLowering()
3857 return DAG.getNode(ISD::UMIN, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
3877 return DAG.getNode(ISD::UMIN, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp717 ISD::SMAX, ISD::UMIN, in initActions()

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