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Searched refs:UMIN (Results 1 – 25 of 39) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3763 { ISD::UMIN, MVT::v32i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3764 { ISD::UMIN, MVT::v64i8, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3853 { ISD::UMIN, MVT::v8i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3854 { ISD::UMIN, MVT::v16i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3855 { ISD::UMIN, MVT::v32i16, { 3, 7, 5, 5 } }, in getIntrinsicInstrCost()
3856 { ISD::UMIN, MVT::v64i8, { 3, 7, 5, 5 } }, in getIntrinsicInstrCost()
3857 { ISD::UMIN, MVT::v4i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3858 { ISD::UMIN, MVT::v2i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
4021 { ISD::UMIN, MVT::v2i64, { 2, 8, 5, 6 } }, in getIntrinsicInstrCost()
4022 { ISD::UMIN, MVT::v4i64, { 2, 8, 5, 8 } }, in getIntrinsicInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h720 UMIN, enumerator
H A DSDPatternMatch.h829 return BinaryOpc_match<LHS, RHS, true>(ISD::UMIN, L, R);
834 return m_AnyOf(BinaryOpc_match<LHS, RHS, true>(ISD::UMIN, L, R),
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsScheduleI6400.td450 (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND|MIN|MAX|UMIN|UMAX)"
H A DMipsScheduleP5600.td636 (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND|MIN|MAX|UMIN|UMAX)"
H A DMipsSEISelLowering.cpp386 setOperationAction(ISD::UMIN, Ty, Legal); in addMSAIntType()
2078 return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2090 return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp108 case ISD::UMIN: in PromoteIntegerResult()
1112 return matcher.getNode(ISD::UMIN, dl, NVT, Add, SatMax); in PromoteIntRes_ADDSUBSHLSAT()
1216 return DAG.getNode(ISD::UMIN, dl, VT, V, in SaturateWidenedDIVFIX()
3052 case ISD::UMIN: in ExpandIntegerResult()
3432 return std::make_pair(ISD::SETLT, ISD::UMIN); in getExpandedMinMaxOps()
3433 case ISD::UMIN: in getExpandedMinMaxOps()
3434 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
3503 if (RHSVal && (N->getOpcode() == ISD::UMIN || N->getOpcode() == ISD::UMAX) && in ExpandIntRes_MINMAX()
3555 case ISD::UMIN: in ExpandIntRes_MINMAX()
H A DSelectionDAGDumper.cpp323 case ISD::UMIN: return "umin"; in getOperationName()
H A DSelectionDAG.cpp426 case ISD::UMIN: in getInverseMinMaxOpcode()
429 return ISD::UMIN; in getInverseMinMaxOpcode()
477 return ISD::UMIN; in getVecReduceBaseOpcode()
4310 case ISD::UMIN: { in computeKnownBits()
4675 Val.getOpcode() == ISD::UMIN || Val.getOpcode() == ISD::UMAX) in isKnownToBeAPowerOfTwo()
4972 case ISD::UMIN: in ComputeNumSignBits()
5549 case ISD::UMIN: in canCreateUndefOrPoison()
5989 case ISD::UMIN: in isKnownNeverZero()
6682 case ISD::UMIN: return C1.ule(C2) ? C1 : C2; in FoldValue()
7574 case ISD::UMIN: in getNode()
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H A DTargetLowering.cpp2310 case ISD::UMIN: in SimplifyDemandedBits()
2344 case ISD::UMIN: in SimplifyDemandedBits()
9662 isOperationLegal(ISD::UMIN, VT)) { in expandABS()
9665 return DAG.getNode(ISD::UMIN, dl, VT, Op, in expandABS()
9710 unsigned MinOpc = IsSigned ? ISD::SMIN : ISD::UMIN; in expandABD()
10618 return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx, Sub); in clampDynamicVectorIndex()
10626 return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx, in clampDynamicVectorIndex()
10755 if (Opcode == ISD::UMIN && isOperationLegal(ISD::SUB, VT) && in expandIntMINMAX()
10810 case ISD::UMIN: in expandIntMINMAX()
10834 if (Opcode == ISD::UADDSAT && isOperationLegal(ISD::UMIN, VT)) { in expandAddSubSat()
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H A DLegalizeVectorOps.cpp451 case ISD::UMIN: in LegalizeOp()
1152 case ISD::UMIN: in Expand()
H A DDAGCombiner.cpp862 TLI.isOperationLegal(ISD::UMIN, LK.second); in hasUMin()
1938 case ISD::UMIN: in visit()
3871 RHS = DAG.getNode(ISD::UMIN, DL, SrcVT, RHS, SatLimit); in getTruncatedUSUBSAT()
3899 if (Op1.getOpcode() == ISD::UMIN && Op1.hasOneUse()) { in foldSubToUSubSat()
3910 Op1.getOperand(0).getOpcode() == ISD::UMIN && in foldSubToUSubSat()
4455 return DAG.getNode(ISD::UMIN, DL, VT, N0, in visitSUB()
6084 bool IsSatBroken = Opcode == ISD::UMIN && N0.getOpcode() == ISD::SMAX; in visitIMINMAX()
6089 case ISD::SMIN: AltOpcode = ISD::UMIN; break; in visitIMINMAX()
6091 case ISD::UMIN: AltOpcode = ISD::SMIN; break; in visitIMINMAX()
6103 if (Opcode == ISD::UMIN) in visitIMINMAX()
[all …]
H A DLegalizeDAG.cpp3738 case ISD::UMIN: in ExpandNode()
3747 case ISD::UMIN: Pred = ISD::SETULT; break; in ExpandNode()
5445 case ISD::UMIN: in PromoteNode()
5471 case ISD::UMIN: in PromoteNode()
H A DLegalizeVectorTypes.cpp167 case ISD::UMIN: in ScalarizeVectorResult()
1331 case ISD::UMIN: case ISD::VP_UMIN: in SplitVectorResult()
3271 DAG.getNode(ISD::UMIN, DL, PtrVT, TrailingBytes, OffsetToV2); in SplitVecRes_VP_SPLICE()
4761 case ISD::UMIN: case ISD::VP_UMIN: in WidenVectorResult()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA64FX.td2138 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_B")>;
2146 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_H")>;
2154 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_S")>;
2162 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_D")>;
H A DAArch64ISelLowering.cpp683 setOperationAction(ISD::UMIN, MVT::i32, Legal); in AArch64TargetLowering()
684 setOperationAction(ISD::UMIN, MVT::i64, Legal); in AArch64TargetLowering()
1312 setOperationAction(ISD::UMIN, VT, Custom); in AArch64TargetLowering()
1544 setOperationAction(ISD::UMIN, VT, Custom); in AArch64TargetLowering()
1853 setOperationAction(ISD::UMIN, MVT::v1i64, Custom); in AArch64TargetLowering()
1854 setOperationAction(ISD::UMIN, MVT::v2i64, Custom); in AArch64TargetLowering()
2073 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
2342 setOperationAction(ISD::UMIN, VT, Default); in addTypeForFixedLengthSVE()
4719 Sat = DAG.getNode(ISD::UMIN, DL, IntVT, NativeCvt, MinC); in LowerVectorFP_TO_INT_SAT()
4720 Sat2 = SrcVal2 ? DAG.getNode(ISD::UMIN, DL, IntVT, NativeCvt2, MinC) : SDValue(); in LowerVectorFP_TO_INT_SAT()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp506 setOperationAction({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX}, MVT::i32, in AMDGPUTargetLowering()
1054 case ISD::UMIN: in isNarrowingProfitable()
3231 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, NewOpr, ConstVal); in LowerCTLZ_CTTZ()
3255 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, OprLo, OprHi); in LowerCTLZ_CTTZ()
3258 NewOpr = DAG.getNode(ISD::UMIN, SL, MVT::i32, NewOpr, Const64); in LowerCTLZ_CTTZ()
3333 ShAmt = DAG.getNode(ISD::UMIN, SL, MVT::i32, ShAmt, MaxShAmt); in LowerINT_TO_FP32()
3355 SDValue Adjust = DAG.getNode(ISD::UMIN, SL, MVT::i32, in LowerINT_TO_FP32()
H A DSIISelLowering.cpp568 setOperationAction({ISD::Constant, ISD::SMIN, ISD::SMAX, ISD::UMIN, in SITargetLowering()
801 ISD::SRA, ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX, in SITargetLowering()
821 ISD::MUL, ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, in SITargetLowering()
968 ISD::UMIN, in SITargetLowering()
974 ISD::UMIN, in SITargetLowering()
4369 DAG.getNode(ISD::UMIN, SL, MVT::i32, NewMode, OffsetEnum); in lowerSET_ROUNDING()
6197 case ISD::UMIN: in LowerOperation()
7197 case ISD::UMIN: in getExtOpcodeForPromotedOp()
7227 Opc == ISD::SMAX || Opc == ISD::UMIN || Opc == ISD::UMAX); in promoteUniformOpToI32()
13813 case ISD::UMIN: in minMaxOpcToMin3Max3Opc()
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def200 VP_PROPERTY_FUNCTIONAL_SDOPC(UMIN)
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp573 case ISD::UMIN: in NVPTXTargetLowering()
652 ISD::UMIN, ISD::UMULO, ISD::UMUL_LOHI, ISD::UREM, in NVPTXTargetLowering()
788 setOperationAction({ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, in NVPTXTargetLowering()
799 setI16x2OperationAction(ISD::UMIN, MVT::v2i16, Legal, Custom); in NVPTXTargetLowering()
2946 case ISD::UMIN: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp220 setOperationAction(ISD::UMIN, T, Legal); in initializeHVXLowering()
327 setOperationAction(ISD::UMIN, T, Custom); in initializeHVXLowering()
3220 case ISD::UMIN: in LowerHvxOperation()
H A DHexagonISelLowering.cpp1628 {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) { in HexagonTargetLowering()
1808 setOperationAction(ISD::UMIN, VT, Legal); in HexagonTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp179 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, MVT::i32, in XtensaTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp798 ISD::SMAX, ISD::UMIN, in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp401 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, XLenVT, in RISCVTargetLowering()
877 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, VT, in RISCVTargetLowering()
1359 {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX, ISD::ABS}, VT, Custom); in RISCVTargetLowering()
1635 setTargetDAGCombine({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}); in RISCVTargetLowering()
6466 Res = DAG.getNode(ISD::UMIN, DL, VT, Res, DAG.getConstant(EltSize, DL, VT)); in lowerCTLZ_CTTZ_ZERO_UNDEF()
6998 OP_CASE(UMIN) in getRISCVVLOp()
7021 VP_CASE(UMIN) // VP_UMIN in getRISCVVLOp()
8150 case ISD::UMIN: in LowerOperation()
8168 unsigned MinOpc = IsSigned ? ISD::SMIN : ISD::UMIN; in LowerOperation()
11260 case ISD::UMIN: in lowerVECREDUCE()
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