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Searched refs:UMAX (Results 1 – 25 of 43) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3761 { ISD::UMAX, MVT::v32i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3762 { ISD::UMAX, MVT::v64i8, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3847 { ISD::UMAX, MVT::v8i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3848 { ISD::UMAX, MVT::v16i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3849 { ISD::UMAX, MVT::v32i16, { 3, 7, 5, 5 } }, in getIntrinsicInstrCost()
3850 { ISD::UMAX, MVT::v64i8, { 3, 7, 5, 5 } }, in getIntrinsicInstrCost()
3851 { ISD::UMAX, MVT::v4i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3852 { ISD::UMAX, MVT::v2i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
4016 { ISD::UMAX, MVT::v2i64, { 2, 8, 5, 6 } }, in getIntrinsicInstrCost()
4017 { ISD::UMAX, MVT::v4i64, { 2, 8, 5, 8 } }, in getIntrinsicInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h721 UMAX, enumerator
H A DSDPatternMatch.h840 return BinaryOpc_match<LHS, RHS, true>(ISD::UMAX, L, R);
845 return m_AnyOf(BinaryOpc_match<LHS, RHS, true>(ISD::UMAX, L, R),
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsScheduleI6400.td450 (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND|MIN|MAX|UMIN|UMAX)"
H A DMipsScheduleP5600.td636 (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND|MIN|MAX|UMIN|UMAX)"
H A DMipsSEISelLowering.cpp385 setOperationAction(ISD::UMAX, Ty, Legal); in addMSAIntType()
2054 return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2066 return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA64FX.td2138 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_B")>;
2146 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_H")>;
2154 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_S")>;
2162 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_D")>;
H A DAArch64SchedOryon.td1461 // IMAX or UMAX in the above line
H A DAArch64ISelLowering.cpp678 setOperationAction(ISD::UMAX, MVT::i32, Legal); in AArch64TargetLowering()
679 setOperationAction(ISD::UMAX, MVT::i64, Legal); in AArch64TargetLowering()
1310 setOperationAction(ISD::UMAX, VT, Custom); in AArch64TargetLowering()
1546 setOperationAction(ISD::UMAX, VT, Custom); in AArch64TargetLowering()
1851 setOperationAction(ISD::UMAX, MVT::v1i64, Custom); in AArch64TargetLowering()
1852 setOperationAction(ISD::UMAX, MVT::v2i64, Custom); in AArch64TargetLowering()
2073 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
2341 setOperationAction(ISD::UMAX, VT, Default); in addTypeForFixedLengthSVE()
5938 return DAG.getNode(ISD::UMAX, DL, Op.getValueType(), Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
7346 case ISD::UMAX: in LowerOperation()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp324 case ISD::UMAX: return "umax"; in getOperationName()
H A DSelectionDAG.cpp427 return ISD::UMAX; in getInverseMinMaxOpcode()
428 case ISD::UMAX: in getInverseMinMaxOpcode()
474 return ISD::UMAX; in getVecReduceBaseOpcode()
4316 case ISD::UMAX: { in computeKnownBits()
4675 Val.getOpcode() == ISD::UMIN || Val.getOpcode() == ISD::UMAX) in isKnownToBeAPowerOfTwo()
4973 case ISD::UMAX: in ComputeNumSignBits()
5550 case ISD::UMAX: in canCreateUndefOrPoison()
5953 case ISD::UMAX: in isKnownNeverZero()
6683 case ISD::UMAX: return C1.uge(C2) ? C1 : C2; in FoldValue()
7566 case ISD::UMAX: in getNode()
[all …]
H A DLegalizeIntegerTypes.cpp109 case ISD::UMAX: Res = PromoteIntRes_UMINUMAX(N); break; in PromoteIntegerResult()
3050 case ISD::UMAX: in ExpandIntegerResult()
3428 return std::make_pair(ISD::SETGT, ISD::UMAX); in getExpandedMinMaxOps()
3429 case ISD::UMAX: in getExpandedMinMaxOps()
3430 return std::make_pair(ISD::SETUGT, ISD::UMAX); in getExpandedMinMaxOps()
3503 if (RHSVal && (N->getOpcode() == ISD::UMIN || N->getOpcode() == ISD::UMAX) && in ExpandIntRes_MINMAX()
3549 case ISD::UMAX: in ExpandIntRes_MINMAX()
H A DLegalizeVectorOps.cpp452 case ISD::UMAX: in LegalizeOp()
1153 case ISD::UMAX: in Expand()
H A DTargetLowering.cpp2311 case ISD::UMAX: { in SimplifyDemandedBits()
2318 (Opc == ISD::SMIN || Opc == ISD::UMAX) ? ISD::OR : ISD::AND; in SimplifyDemandedBits()
2351 case ISD::UMAX: in SimplifyDemandedBits()
9709 unsigned MaxOpc = IsSigned ? ISD::SMAX : ISD::UMAX; in expandABD()
10745 if (Opcode == ISD::UMAX && llvm::isOneOrOneSplat(Op1, true) && BoolVT == VT && in expandIntMINMAX()
10763 if (Opcode == ISD::UMAX && isOperationLegal(ISD::ADD, VT) && in expandIntMINMAX()
10808 case ISD::UMAX: in expandIntMINMAX()
10828 if (Opcode == ISD::USUBSAT && isOperationLegal(ISD::UMAX, VT)) { in expandAddSubSat()
10829 SDValue Max = DAG.getNode(ISD::UMAX, dl, VT, LHS, RHS); in expandAddSubSat()
H A DLegalizeDAG.cpp3739 case ISD::UMAX: { in ExpandNode()
3746 case ISD::UMAX: Pred = ISD::SETUGT; break; in ExpandNode()
5446 case ISD::UMAX: in PromoteNode()
5472 case ISD::UMAX: in PromoteNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp569 ISD::UMAX, ISD::UADDSAT, ISD::USUBSAT}, in SITargetLowering()
801 ISD::SRA, ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX, in SITargetLowering()
822 ISD::UMAX, ISD::UADDSAT, ISD::SADDSAT, ISD::USUBSAT, in SITargetLowering()
969 ISD::UMAX, in SITargetLowering()
975 ISD::UMAX, in SITargetLowering()
6198 case ISD::UMAX: in LowerOperation()
7198 case ISD::UMAX: in getExtOpcodeForPromotedOp()
7227 Opc == ISD::SMAX || Opc == ISD::UMIN || Opc == ISD::UMAX); in promoteUniformOpToI32()
13803 case ISD::UMAX: in minMaxOpcToMin3Max3Opc()
13965 case ISD::UMAX: in supportsMin3Max3()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def207 VP_PROPERTY_FUNCTIONAL_SDOPC(UMAX)
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp574 case ISD::UMAX: in NVPTXTargetLowering()
651 ISD::UDIV, ISD::UDIVREM, ISD::UINT_TO_FP, ISD::UMAX, in NVPTXTargetLowering()
788 setOperationAction({ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, in NVPTXTargetLowering()
800 setI16x2OperationAction(ISD::UMAX, MVT::v2i16, Legal, Custom); in NVPTXTargetLowering()
2947 case ISD::UMAX: in LowerOperation()
/freebsd/sys/dev/usb/
H A Dusbdevs690 vendor UMAX 0x1606 UMAX Data Systems
4912 /* UMAX products */
4913 product UMAX ASTRA1236U 0x0002 Astra 1236U Scanner
4914 product UMAX ASTRA1220U 0x0010 Astra 1220U Scanner
4915 product UMAX ASTRA2000U 0x0030 Astra 2000U Scanner
4916 product UMAX ASTRA2100U 0x0130 Astra 2100U Scanner
4917 product UMAX ASTRA2200U 0x0230 Astra 2200U Scanner
4918 product UMAX ASTRA3400 0x0060 Astra 3400 Scanner
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp221 setOperationAction(ISD::UMAX, T, Legal); in initializeHVXLowering()
328 setOperationAction(ISD::UMAX, T, Custom); in initializeHVXLowering()
3221 case ISD::UMAX: in LowerHvxOperation()
H A DHexagonISelLowering.cpp1628 {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) { in HexagonTargetLowering()
1809 setOperationAction(ISD::UMAX, VT, Legal); in HexagonTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp179 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, MVT::i32, in XtensaTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp799 ISD::UMAX, ISD::ABS, in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp401 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, XLenVT, in RISCVTargetLowering()
877 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, VT, in RISCVTargetLowering()
1359 {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX, ISD::ABS}, VT, Custom); in RISCVTargetLowering()
1635 setTargetDAGCombine({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}); in RISCVTargetLowering()
6999 OP_CASE(UMAX) in getRISCVVLOp()
7022 VP_CASE(UMAX) // VP_UMAX in getRISCVVLOp()
8151 case ISD::UMAX: in LowerOperation()
8167 unsigned MaxOpc = IsSigned ? ISD::SMAX : ISD::UMAX; in LowerOperation()
11259 case ISD::UMAX: in lowerVECREDUCE()
14809 case ISD::UMAX: in getVecReduceOpcode()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp298 setOperationAction({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}, VT, in LoongArchTargetLowering()
365 setOperationAction({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}, VT, in LoongArchTargetLowering()
5312 return DAG.getNode(ISD::UMAX, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
5332 return DAG.getNode(ISD::UMAX, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()

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