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Searched refs:UMAX (Results 1 – 25 of 40) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3603 { ISD::UMAX, MVT::v32i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3604 { ISD::UMAX, MVT::v64i8, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3669 { ISD::UMAX, MVT::v8i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3670 { ISD::UMAX, MVT::v16i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3671 { ISD::UMAX, MVT::v32i16, { 3, 7, 5, 5 } }, in getIntrinsicInstrCost()
3672 { ISD::UMAX, MVT::v64i8, { 3, 7, 5, 5 } }, in getIntrinsicInstrCost()
3673 { ISD::UMAX, MVT::v4i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3674 { ISD::UMAX, MVT::v2i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3817 { ISD::UMAX, MVT::v2i64, { 2, 8, 5, 6 } }, in getIntrinsicInstrCost()
3818 { ISD::UMAX, MVT::v4i64, { 2, 8, 5, 8 } }, in getIntrinsicInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h699 UMAX, enumerator
H A DSDPatternMatch.h589 return BinaryOpc_match<LHS, RHS, true>(ISD::UMAX, L, R);
H A DTargetLowering.h2887 case ISD::UMAX: in isCommutativeBinOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA64FX.td2138 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_B")>;
2146 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_H")>;
2154 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_S")>;
2162 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_D")>;
H A DAArch64ISelLowering.cpp664 setOperationAction(ISD::UMAX, MVT::i32, Legal); in AArch64TargetLowering()
665 setOperationAction(ISD::UMAX, MVT::i64, Legal); in AArch64TargetLowering()
1258 setOperationAction(ISD::UMAX, VT, Custom); in AArch64TargetLowering()
1454 setOperationAction(ISD::UMAX, VT, Custom); in AArch64TargetLowering()
1722 setOperationAction(ISD::UMAX, MVT::v1i64, Custom); in AArch64TargetLowering()
1723 setOperationAction(ISD::UMAX, MVT::v2i64, Custom); in AArch64TargetLowering()
1904 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
2104 setOperationAction(ISD::UMAX, VT, Default); in addTypeForFixedLengthSVE()
5702 return DAG.getNode(ISD::UMAX, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
6878 case ISD::UMAX: in LowerOperation()
[all …]
H A DAArch64SchedOryon.td1461 // IMAX or UMAX in the above line
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp307 case ISD::UMAX: return "umax"; in getOperationName()
H A DLegalizeIntegerTypes.cpp106 case ISD::UMAX: Res = PromoteIntRes_UMINUMAX(N); break; in PromoteIntegerResult()
2867 case ISD::UMAX: in ExpandIntegerResult()
3245 return std::make_pair(ISD::SETGT, ISD::UMAX); in getExpandedMinMaxOps()
3246 case ISD::UMAX: in getExpandedMinMaxOps()
3247 return std::make_pair(ISD::SETUGT, ISD::UMAX); in getExpandedMinMaxOps()
3306 if (RHSVal && (N->getOpcode() == ISD::UMIN || N->getOpcode() == ISD::UMAX) && in ExpandIntRes_MINMAX()
3352 case ISD::UMAX: in ExpandIntRes_MINMAX()
H A DLegalizeVectorOps.cpp438 case ISD::UMAX: in LegalizeOp()
1022 case ISD::UMAX: in Expand()
H A DSelectionDAG.cpp462 return ISD::UMAX; in getVecReduceBaseOpcode()
4079 case ISD::UMAX: { in computeKnownBits()
4404 Val.getOpcode() == ISD::UMIN || Val.getOpcode() == ISD::UMAX) in isKnownToBeAPowerOfTwo()
4702 case ISD::UMAX: in ComputeNumSignBits()
5266 case ISD::UMAX: in canCreateUndefOrPoison()
5556 case ISD::UMAX: in isKnownNeverZero()
6269 case ISD::UMAX: return C1.uge(C2) ? C1 : C2; in FoldValue()
7019 case ISD::UMAX: in getNode()
11899 case ISD::UMAX: in isNeutralConstant()
13161 case ISD::UMAX: in getNeutralElement()
H A DTargetLowering.cpp2243 case ISD::UMAX: { in SimplifyDemandedBits()
2250 (Opc == ISD::SMIN || Opc == ISD::UMAX) ? ISD::OR : ISD::AND; in SimplifyDemandedBits()
2283 case ISD::UMAX: in SimplifyDemandedBits()
9266 unsigned MaxOpc = IsSigned ? ISD::SMAX : ISD::UMAX; in expandABD()
10253 if (Opcode == ISD::UMAX && llvm::isOneOrOneSplat(Op1, true) && BoolVT == VT && in expandIntMINMAX()
10271 if (Opcode == ISD::UMAX && isOperationLegal(ISD::ADD, VT) && in expandIntMINMAX()
10316 case ISD::UMAX: in expandIntMINMAX()
10336 if (Opcode == ISD::USUBSAT && isOperationLegal(ISD::UMAX, VT)) { in expandAddSubSat()
10337 SDValue Max = DAG.getNode(ISD::UMAX, dl, VT, LHS, RHS); in expandAddSubSat()
H A DLegalizeDAG.cpp3616 case ISD::UMAX: { in ExpandNode()
3623 case ISD::UMAX: Pred = ISD::SETUGT; break; in ExpandNode()
5235 case ISD::UMAX: in PromoteNode()
5261 case ISD::UMAX: in PromoteNode()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def235 VP_PROPERTY_FUNCTIONAL_SDOPC(UMAX)
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp472 case ISD::UMAX: in NVPTXTargetLowering()
540 ISD::UDIV, ISD::UDIVREM, ISD::UINT_TO_FP, ISD::UMAX, in NVPTXTargetLowering()
680 setOperationAction(ISD::UMAX, Ty, Legal); in NVPTXTargetLowering()
690 setI16x2OperationAction(ISD::UMAX, MVT::v2i16, Legal, Custom); in NVPTXTargetLowering()
2806 case ISD::UMAX: in LowerOperation()
/freebsd/sys/dev/usb/
H A Dusbdevs690 vendor UMAX 0x1606 UMAX Data Systems
4889 /* UMAX products */
4890 product UMAX ASTRA1236U 0x0002 Astra 1236U Scanner
4891 product UMAX ASTRA1220U 0x0010 Astra 1220U Scanner
4892 product UMAX ASTRA2000U 0x0030 Astra 2000U Scanner
4893 product UMAX ASTRA2100U 0x0130 Astra 2100U Scanner
4894 product UMAX ASTRA2200U 0x0230 Astra 2200U Scanner
4895 product UMAX ASTRA3400 0x0060 Astra 3400 Scanner
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td636 (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND|MIN|MAX|UMIN|UMAX)"
H A DMipsSEISelLowering.cpp346 setOperationAction(ISD::UMAX, Ty, Legal); in addMSAIntType()
2010 return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2022 return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
H A DMipsScheduleGeneric.td1621 (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND|MIN|MAX|UMIN|UMAX)"
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp553 ISD::UMAX, ISD::UADDSAT, ISD::USUBSAT}, in SITargetLowering()
775 ISD::SRA, ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX, in SITargetLowering()
795 ISD::UMAX, ISD::UADDSAT, ISD::SADDSAT, ISD::USUBSAT, in SITargetLowering()
909 ISD::UMAX, in SITargetLowering()
5851 case ISD::UMAX: in LowerOperation()
13030 case ISD::UMAX: in minMaxOpcToMin3Max3Opc()
13164 case ISD::UMAX: in supportsMin3Max3()
13226 if (Opc == ISD::UMIN && Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) { in performMinMaxCombine()
13231 if (Opc == ISD::UMAX && Op0.getOpcode() == ISD::UMIN && Op0.hasOneUse()) { in performMinMaxCombine()
13412 case ISD::UMAX: in performExtractVectorEltCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp217 setOperationAction(ISD::UMAX, T, Legal); in initializeHVXLowering()
322 setOperationAction(ISD::UMAX, T, Custom); in initializeHVXLowering()
3184 case ISD::UMAX: in LowerHvxOperation()
H A DHexagonISelLowering.cpp1560 {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) { in HexagonTargetLowering()
1735 setOperationAction(ISD::UMAX, VT, Legal); in HexagonTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp259 setOperationAction({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}, VT, in LoongArchTargetLowering()
306 setOperationAction({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}, VT, in LoongArchTargetLowering()
3817 return DAG.getNode(ISD::UMAX, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
3837 return DAG.getNode(ISD::UMAX, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp378 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, XLenVT, in RISCVTargetLowering()
381 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, MVT::i32, in RISCVTargetLowering()
829 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, VT, in RISCVTargetLowering()
1240 {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX, ISD::ABS}, VT, Custom); in RISCVTargetLowering()
1458 setOperationAction(ISD::UMAX, XLenVT, Legal); in RISCVTargetLowering()
1480 setTargetDAGCombine({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}); in RISCVTargetLowering()
5993 OP_CASE(UMAX) in getRISCVVLOp()
6016 VP_CASE(UMAX) // VP_UMAX in getRISCVVLOp()
7034 case ISD::UMAX: in LowerOperation()
7056 unsigned MaxOpc = IsSigned ? ISD::SMAX : ISD::UMAX; in LowerOperation()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp718 ISD::UMAX, ISD::ABS, in initActions()

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