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Searched refs:UADDLV (Results 1 – 6 of 6) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td391 def : InstRW<[CyWriteV3], (instregex "SADDLV","UADDLV")>;
H A DAArch64SchedThunderX2T99.td1367 def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SADDLV","^UADDLV")>;
H A DAArch64SchedThunderX3T110.td1475 def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^SADDLV","^UADDLV")>;
H A DAArch64ISelLowering.cpp6349 IntNo == Intrinsic::aarch64_neon_uaddlv ? AArch64ISD::UADDLV in LowerINTRINSIC_WO_CHAIN()
18472 return DAG.getNode(AArch64ISD::UADDLV, SDLoc(A), VT, Concat); in performUADDVZextCombine()
18475 DAG.getNode(AArch64ISD::UADDLV, SDLoc(A), MVT::v4i32, Concat); in performUADDVZextCombine()
26663 SDValue UADDLV = EXTRACT_VEC_ELT.getOperand(0); in performScalarToVectorCombine() local
26664 if (UADDLV.getOpcode() != AArch64ISD::UADDLV || in performScalarToVectorCombine()
26665 UADDLV.getValueType() != MVT::v4i32 || in performScalarToVectorCombine()
26666 UADDLV.getOperand(0).getValueType() != MVT::v8i8) in performScalarToVectorCombine()
26672 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, UADDLV, in performScalarToVectorCombine()
H A DAArch64SchedA64FX.td1503 def : InstRW<[A64FXWrite_ADDLV1], (instregex "^SADDLV", "^UADDLV")>;
H A DAArch64InstrInfo.td1050 def AArch64uaddlv : SDNode<"AArch64ISD::UADDLV", SDT_AArch64uaddlp>;
7698 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
7737 defm : SIMDAcrossLaneLongPairIntrinsic<"UADDLV", AArch64uaddlp>;
7757 defm : SIMDAcrossLaneLongPairIntrinsicGISel<"UADDLV", AArch64uaddlp>;
7786 defm : SIMDAcrossLaneLongReductionIntrinsic<"UADDLV", AArch64uaddlv>;
7983 // The UADDLV v2i32 gets mapped to UADDLP.