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Searched refs:UADDLV (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h274 UADDLV, enumerator
H A DAArch64SchedCyclone.td391 def : InstRW<[CyWriteV3], (instregex "SADDLV","UADDLV")>;
H A DAArch64ISelLowering.cpp2670 MAKE_CASE(AArch64ISD::UADDLV) in getTargetNodeName()
6056 SDValue UADDLV = in LowerINTRINSIC_WO_CHAIN() local
6057 DAG.getNode(AArch64ISD::UADDLV, dl, MVT::v4i32, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
6059 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, UADDLV, in LowerINTRINSIC_WO_CHAIN()
10068 SDValue UaddLV = DAG.getNode(AArch64ISD::UADDLV, DL, MVT::v4i32, CtPop); in LowerCTPOP_PARITY()
10083 SDValue UaddLV = DAG.getNode(AArch64ISD::UADDLV, DL, MVT::v4i32, CtPop); in LowerCTPOP_PARITY()
17905 return DAG.getNode(AArch64ISD::UADDLV, SDLoc(A), VT, Concat); in performUADDVZextCombine()
17908 DAG.getNode(AArch64ISD::UADDLV, SDLoc(A), MVT::v4i32, Concat); in performUADDVZextCombine()
25238 SDValue UADDLV = EXTRACT_VEC_ELT.getOperand(0); in performScalarToVectorCombine() local
25239 if (UADDLV.getOpcode() != AArch64ISD::UADDLV || in performScalarToVectorCombine()
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H A DAArch64SchedThunderX2T99.td1367 def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^SADDLV","^UADDLV")>;
H A DAArch64SchedThunderX3T110.td1475 def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^SADDLV","^UADDLV")>;
H A DAArch64InstrInfo.td863 def AArch64uaddlv : SDNode<"AArch64ISD::UADDLV", SDT_AArch64uaddlp>;
7126 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
7152 defm : SIMDAcrossLaneLongPairIntrinsic<"UADDLV", AArch64uaddlp>;
7172 defm : SIMDAcrossLaneLongPairIntrinsicGISel<"UADDLV", AArch64uaddlp>;
7212 defm : SIMDAcrossLaneLongReductionIntrinsic<"UADDLV", AArch64uaddlv>;
7468 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
H A DAArch64SchedA64FX.td1503 def : InstRW<[A64FXWrite_ADDLV1], (instregex "^SADDLV", "^UADDLV")>;