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Searched refs:Tmp2 (Results 1 – 25 of 27) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DIntrinsicLowering.cpp65 Value *Tmp2 = Builder.CreateLShr(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
67 V = Builder.CreateOr(Tmp1, Tmp2, "bswap.i16"); in LowerBSWAP()
75 Value *Tmp2 = Builder.CreateLShr(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
82 Tmp2 = Builder.CreateAnd(Tmp2, in LowerBSWAP()
86 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or2"); in LowerBSWAP()
87 V = Builder.CreateOr(Tmp4, Tmp2, "bswap.i32"); in LowerBSWAP()
104 Value* Tmp2 = Builder.CreateLShr(V, in LowerBSWAP() local
130 Tmp2 = Builder.CreateAnd(Tmp2, in LowerBSWAP()
137 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or4"); in LowerBSWAP()
139 Tmp4 = Builder.CreateOr(Tmp4, Tmp2, "bswap.or6"); in LowerBSWAP()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp1739 SDValue Tmp2 = SDValue(Node, 1); in ExpandDYNAMIC_STACKALLOC() local
1747 SDValue Size = Tmp2.getOperand(1); in ExpandDYNAMIC_STACKALLOC()
1763 Tmp2 = DAG.getCALLSEQ_END(Chain, 0, 0, SDValue(), dl); in ExpandDYNAMIC_STACKALLOC()
1766 Results.push_back(Tmp2); in ExpandDYNAMIC_STACKALLOC()
3058 SDValue Tmp1, Tmp2, Tmp3, Tmp4; in ExpandNode() local
3399 if (TLI.expandUINT_TO_FP(Node, Tmp1, Tmp2, DAG)) { in ExpandNode()
3402 Results.push_back(Tmp2); in ExpandNode()
3408 if ((Tmp1 = ExpandLegalINT_TO_FP(Node, Tmp2))) { in ExpandNode()
3411 Results.push_back(Tmp2); in ExpandNode()
3426 if (TLI.expandFP_TO_UINT(Node, Tmp1, Tmp2, DAG)) in ExpandNode()
[all …]
H A DTargetLowering.cpp8143 SDValue Tmp2, Tmp3; in expandShiftParts() local
8145 Tmp2 = DAG.getNode(ISD::FSHL, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
8148 Tmp2 = DAG.getNode(ISD::FSHR, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
8161 Hi = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp3, Tmp2); in expandShiftParts()
8164 Lo = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp3, Tmp2); in expandShiftParts()
8930 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5; in expandVPCTPOP() local
8940 Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Op, Mask33, Mask, VL); in expandVPCTPOP()
8945 Op = DAG.getNode(ISD::VP_ADD, dl, VT, Tmp2, Tmp3, Mask, VL); in expandVPCTPOP()
9370 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; in expandBSWAP() local
9382 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); in expandBSWAP()
[all …]
H A DSelectionDAG.cpp2420 SDValue Tmp2 = Node->getOperand(1); in expandVAArg() local
2424 Tmp2, MachinePointerInfo(V)); in expandVAArg()
2443 getStore(VAListLoad.getValue(1), dl, Tmp1, Tmp2, MachinePointerInfo(V)); in expandVAArg()
4458 unsigned Tmp, Tmp2; in ComputeNumSignBits() local
4504 Tmp2 = T.getNumSignBits(); in ComputeNumSignBits()
4506 Tmp2 = ComputeNumSignBits(SrcOp, Depth + 1); in ComputeNumSignBits()
4512 Tmp2 = (Tmp2 > ExtraBits ? Tmp2 - ExtraBits : 1); in ComputeNumSignBits()
4515 Tmp = std::min(Tmp, Tmp2); in ComputeNumSignBits()
4533 Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedRHS, Depth + 1); in ComputeNumSignBits()
4534 Tmp = std::min(Tmp, Tmp2); in ComputeNumSignBits()
[all …]
H A DLegalizeFloatTypes.cpp2128 SDValue Tmp1, Tmp2, Tmp3, OutputChain; in FloatExpandSetCCOperands() local
2132 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()), LHSLo, in FloatExpandSetCCOperands()
2134 OutputChain = Tmp2->getNumValues() > 1 ? Tmp2.getValue(1) : SDValue(); in FloatExpandSetCCOperands()
2135 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
2140 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), LHSHi, in FloatExpandSetCCOperands()
2142 OutputChain = Tmp2->getNumValues() > 1 ? Tmp2.getValue(1) : SDValue(); in FloatExpandSetCCOperands()
2143 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4190 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchBEXTRFromAndImm() local
4191 if (tryFoldLoad(Node, N0.getNode(), Input, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in matchBEXTRFromAndImm()
4193 Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Control, Input.getOperand(0)}; in matchBEXTRFromAndImm()
4227 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPISTR() local
4228 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPISTR()
4229 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPISTR()
4260 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPESTR() local
4261 if (MayFoldLoad && tryFoldLoad(Node, N2, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPESTR()
4262 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPESTR()
4553 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchVPTERNLOG() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp123 Value *Tmp2 = Builder.CreateXor(Tmp, Dividend); in generateSignedDivisionCode() local
124 Value *U_Dvnd = Builder.CreateSub(Tmp2, Tmp); in generateSignedDivisionCode()
252 Value *Tmp2 = Builder.CreateSub(MSB, SR); in generateUnsignedDivisionCode() local
253 Value *Q = Builder.CreateShl(Dividend, Tmp2); in generateUnsignedDivisionCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2030 Register Tmp2 = MRI.createVirtualRegister(RC); in prepareMBB() local
2042 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareMBB()
2047 .addReg(Tmp2, getKillRegState(true)) in prepareMBB()
2058 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareMBB()
2062 .addReg(Tmp2, getKillRegState(true)) in prepareMBB()
2094 Register Tmp2 = MRI.createVirtualRegister(RC); in prepareSymbol() local
2103 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
2108 .addReg(Tmp2, getKillRegState(true)) in prepareSymbol()
2112 Register Tmp2 = MRI.createVirtualRegister(RC); in prepareSymbol() local
2123 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
[all …]
/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/
H A DExprEngineC.cpp49 ExplodedNodeSet Tmp2; in VisitBinaryOperator() local
74 evalStore(Tmp2, B, LHS, *it, state->BindExpr(B, LCtx, ExprVal), in VisitBinaryOperator()
80 StmtNodeBuilder Bldr(*it, Tmp2, *currBldrCtx); in VisitBinaryOperator()
185 evalStore(Tmp2, B, LHS, N, state, location, LHSVal); in VisitBinaryOperator()
190 getCheckerManager().runCheckersForPostStmt(Dst, Tmp2, B, *this); in VisitBinaryOperator()
H A DCheckerManager.cpp123 ExplodedNodeSet Tmp1, Tmp2; in expandGraphWithCheckers() local
131 CurrSet = (PrevSet == &Tmp1) ? &Tmp2 : &Tmp1; in expandGraphWithCheckers()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp1942 SmallVector<MachineOperand,1> Tmp2; in createPreheaderForLoop() local
1949 Tmp2.clear(); in createPreheaderForLoop()
1950 bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp2, false); in createPreheaderForLoop()
1953 if (TB != Header && (Tmp2.empty() || FB != Header)) in createPreheaderForLoop()
1962 bool LatchNotAnalyzed = TII->analyzeBranch(*Latch, TB, FB, Tmp2, false); in createPreheaderForLoop()
H A DHexagonSplitDouble.cpp689 auto *Tmp2 = in splitMemRef() local
691 HighI->addMemOperand(MF, Tmp2); in splitMemRef()
H A DHexagonISelLoweringHVX.cpp2465 SDValue Tmp2 = DAG.getNode(ShRight, dl, IntTy, Tmp0, AmtM1); in emitHvxShiftRightRnd()
2466 SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, IntTy, Tmp2, Rup); in emitHvxShiftRightRnd() local
2468 SDValue Eq = DAG.getSetCC(dl, PredTy, Tmp1, Tmp2, ISD::SETEQ); in emitHvxShiftRightRnd()
2470 SDValue Tmp4 = DAG.getNode(ShRight, dl, IntTy, {Tmp2, One}); in emitHvxShiftRightRnd()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DValueTracking.cpp3787 unsigned Tmp, Tmp2; in ComputeNumSignBitsImpl() local
3885 Tmp2 = ShAmt->getZExtValue(); in ComputeNumSignBitsImpl()
3886 return Tmp - Tmp2; in ComputeNumSignBitsImpl()
3896 Tmp2 = ComputeNumSignBits(U->getOperand(1), DemandedElts, Depth + 1, Q); in ComputeNumSignBitsImpl()
3897 FirstAnswer = std::min(Tmp, Tmp2); in ComputeNumSignBitsImpl()
3915 Tmp2 = ComputeNumSignBits(U->getOperand(2), DemandedElts, Depth + 1, Q); in ComputeNumSignBitsImpl()
3916 return std::min(Tmp, Tmp2); in ComputeNumSignBitsImpl()
3942 Tmp2 = ComputeNumSignBits(U->getOperand(1), DemandedElts, Depth + 1, Q); in ComputeNumSignBitsImpl()
3943 if (Tmp2 == 1) in ComputeNumSignBitsImpl()
3945 return std::min(Tmp, Tmp2) - 1; in ComputeNumSignBitsImpl()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2470 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); in LowerShiftRightParts() local
2471 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftRightParts()
2530 SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); in LowerShiftLeftParts() local
2531 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftLeftParts()
2834 SDValue Tmp2 = Node->getOperand(1); in LowerVAARG() local
2838 Tmp1, Tmp2, MachinePointerInfo(V)); in LowerVAARG()
2857 Tmp1 = DAG.getStore(VAListLoad.getValue(1), DL, Tmp1, Tmp2, in LowerVAARG()
3099 SDValue Tmp2 = ST->getBasePtr(); in LowerSTOREi1() local
3104 DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), MVT::i8, in LowerSTOREi1()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2445 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); in LowerFTRUNC() local
2447 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2); in LowerFTRUNC()
2464 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFROUNDEVEN() local
2475 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2); in LowerFROUNDEVEN()
5836 unsigned Tmp2 = DAG.ComputeNumSignBits(Op.getOperand(2), Depth + 1); in ComputeNumSignBitsForTargetNode() local
5837 if (Tmp2 == 1) in ComputeNumSignBitsForTargetNode()
5848 return std::min({Tmp0, Tmp1, Tmp2}); in ComputeNumSignBitsForTargetNode()
5876 unsigned Tmp2 = Analysis.computeNumSignBits(Src2, DemandedElts, Depth + 1); in computeNumSignBitsForTargetInstr() local
5877 if (Tmp2 == 1) in computeNumSignBitsForTargetInstr()
5885 return std::min({Tmp0, Tmp1, Tmp2}); in computeNumSignBitsForTargetInstr()
H A DAMDGPULegalizerInfo.cpp2436 auto Tmp2 = B.buildFSub(Ty, Tmp1, CopySign); in legalizeFroundeven() local
2442 B.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2); in legalizeFroundeven()
4868 auto Tmp2 = B.buildFMA(ResTy, NegY, Ret, X); in legalizeFastUnsafeFDIV64() local
4870 B.buildFMA(Res, Tmp2, R, Ret); in legalizeFastUnsafeFDIV64()
H A DSIInstrInfo.cpp710 Register Tmp2 = RS.scavengeRegisterBackwards(AMDGPU::VGPR_32RegClass, MI, in indirectCopyToAGPR() local
713 if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs) in indirectCopyToAGPR()
715 Tmp = Tmp2; in indirectCopyToAGPR()
H A DSIISelLowering.cpp3967 SDValue Tmp2 = Op.getValue(1); in lowerDYNAMIC_STACKALLOCImpl() local
3977 SDValue Size = Tmp2.getOperand(1); in lowerDYNAMIC_STACKALLOCImpl()
4000 Tmp2 = DAG.getCALLSEQ_END(Chain, 0, 0, SDValue(), dl); in lowerDYNAMIC_STACKALLOCImpl()
4002 return DAG.getMergeValues({Tmp1, Tmp2}, dl); in lowerDYNAMIC_STACKALLOCImpl()
10520 SDValue Tmp2 = DAG.getNode(ISD::FMA, SL, VT, NegY, Ret, X); in lowerFastUnsafeFDIV64() local
10521 return DAG.getNode(ISD::FMA, SL, VT, Tmp2, R, Ret); in lowerFastUnsafeFDIV64()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGExprComplex.cpp1092 llvm::Value *Tmp2 = Builder.CreateMul(LHSi, RHSi); // b*d in EmitBinDiv() local
1093 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd in EmitBinDiv()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp8223 MachineInstrBuilder Tmp2; in lowerBitreverse() local
8226 Tmp2 = MIRBuilder.buildShl(Ty, Src, ShAmt); in lowerBitreverse()
8229 Tmp2 = MIRBuilder.buildLShr(Ty, Src, ShAmt); in lowerBitreverse()
8233 Tmp2 = MIRBuilder.buildAnd(Ty, Tmp2, Mask); in lowerBitreverse()
8235 Tmp = Tmp2; in lowerBitreverse()
8237 Tmp = MIRBuilder.buildOr(Ty, Tmp, Tmp2); in lowerBitreverse()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp6270 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
6272 SDValue(Tmp2, 0))); in Select()
6284 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
6286 SDValue(Tmp2, 0))); in Select()
H A DPPCISelLowering.cpp9117 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); in LowerSHL_PARTS() local
9119 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); in LowerSHL_PARTS()
9146 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); in LowerSRL_PARTS() local
9148 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRL_PARTS()
9174 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); in LowerSRA_PARTS() local
9176 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRA_PARTS()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp6931 SDValue Tmp2 = Op.getOperand(1); in LowerOperation()
6941 DAG.getNode(ISD::SETCC, DL, CCVT, Tmp1, Tmp2, CC, Op->getFlags()); in LowerOperation()
11034 SDValue Tmp2 = DAG.getNode(ISD::STRICT_FSETCCS, DL, VTList, Chain, Op2, in lowerVectorStrictFSetcc()
11037 Tmp1.getValue(1), Tmp2.getValue(1)); in lowerVectorStrictFSetcc()
11038 // Tmp1 and Tmp2 might be the same node. in lowerVectorStrictFSetcc()
11039 if (Tmp1 != Tmp2) in lowerVectorStrictFSetcc()
11040 Tmp1 = DAG.getNode(ISD::AND, DL, VT, Tmp1, Tmp2); in lowerVectorStrictFSetcc()
17961 unsigned Tmp2 = in ComputeNumSignBitsForTargetNode()
17963 return std::min(Tmp, Tmp2); in ComputeNumSignBitsForTargetNode()
6929 SDValue Tmp2 = Op.getOperand(1); LowerOperation() local
11032 SDValue Tmp2 = DAG.getNode(ISD::STRICT_FSETCCS, DL, VTList, Chain, Op2, lowerVectorStrictFSetcc() local
17958 unsigned Tmp2 = ComputeNumSignBitsForTargetNode() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp4184 SDValue Tmp2 = CurDAG->getTargetConstant(CC, dl, MVT::i32); in Select() local
4185 SDValue Ops[] = { N1, Tmp2, N3, Chain, InGlue }; in Select()

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