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Searched refs:Tmp2 (Results 1 – 25 of 28) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DIntrinsicLowering.cpp65 Value *Tmp2 = Builder.CreateLShr(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
67 V = Builder.CreateOr(Tmp1, Tmp2, "bswap.i16"); in LowerBSWAP()
75 Value *Tmp2 = Builder.CreateLShr(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
82 Tmp2 = Builder.CreateAnd(Tmp2, in LowerBSWAP()
86 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or2"); in LowerBSWAP()
87 V = Builder.CreateOr(Tmp4, Tmp2, "bswap.i32"); in LowerBSWAP()
104 Value* Tmp2 = Builder.CreateLShr(V, in LowerBSWAP() local
130 Tmp2 = Builder.CreateAnd(Tmp2, in LowerBSWAP()
137 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or4"); in LowerBSWAP()
139 Tmp4 = Builder.CreateOr(Tmp4, Tmp2, "bswap.or6"); in LowerBSWAP()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp1803 SDValue Tmp2 = SDValue(Node, 1); in ExpandDYNAMIC_STACKALLOC() local
1811 SDValue Size = Tmp2.getOperand(1); in ExpandDYNAMIC_STACKALLOC()
1827 Tmp2 = DAG.getCALLSEQ_END(Chain, 0, 0, SDValue(), dl); in ExpandDYNAMIC_STACKALLOC()
1830 Results.push_back(Tmp2); in ExpandDYNAMIC_STACKALLOC()
3088 SDValue Tmp1, Tmp2, Tmp3, Tmp4; in ExpandNode() local
3456 if (TLI.expandUINT_TO_FP(Node, Tmp1, Tmp2, DAG)) { in ExpandNode()
3459 Results.push_back(Tmp2); in ExpandNode()
3465 if ((Tmp1 = ExpandLegalINT_TO_FP(Node, Tmp2))) { in ExpandNode()
3468 Results.push_back(Tmp2); in ExpandNode()
3483 if (TLI.expandFP_TO_UINT(Node, Tmp1, Tmp2, DAG)) in ExpandNode()
[all …]
H A DTargetLowering.cpp8361 SDValue Tmp2, Tmp3; in expandShiftParts() local
8363 Tmp2 = DAG.getNode(ISD::FSHL, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
8366 Tmp2 = DAG.getNode(ISD::FSHR, dl, VT, ShOpHi, ShOpLo, ShAmt); in expandShiftParts()
8379 Hi = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp3, Tmp2); in expandShiftParts()
8382 Lo = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp3, Tmp2); in expandShiftParts()
9335 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5; in expandVPCTPOP() local
9345 Tmp2 = DAG.getNode(ISD::VP_AND, dl, VT, Op, Mask33, Mask, VL); in expandVPCTPOP()
9350 Op = DAG.getNode(ISD::VP_ADD, dl, VT, Tmp2, Tmp3, Mask, VL); in expandVPCTPOP()
9865 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; in expandBSWAP() local
9877 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); in expandBSWAP()
[all …]
H A DSelectionDAG.cpp2658 SDValue Tmp2 = Node->getOperand(1); in expandVAArg() local
2662 Tmp2, MachinePointerInfo(V)); in expandVAArg()
2681 getStore(VAListLoad.getValue(1), dl, Tmp1, Tmp2, MachinePointerInfo(V)); in expandVAArg()
4729 unsigned Tmp, Tmp2; in ComputeNumSignBits() local
4775 Tmp2 = T.getNumSignBits(); in ComputeNumSignBits()
4777 Tmp2 = ComputeNumSignBits(SrcOp, Depth + 1); in ComputeNumSignBits()
4783 Tmp2 = (Tmp2 > ExtraBits ? Tmp2 - ExtraBits : 1); in ComputeNumSignBits()
4786 Tmp = std::min(Tmp, Tmp2); in ComputeNumSignBits()
4804 Tmp2 = ComputeNumSignBits(Op.getOperand(1), DemandedRHS, Depth + 1); in ComputeNumSignBits()
4805 Tmp = std::min(Tmp, Tmp2); in ComputeNumSignBits()
[all …]
H A DLegalizeFloatTypes.cpp2344 SDValue Tmp1, Tmp2, Tmp3, OutputChain; in FloatExpandSetCCOperands() local
2348 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()), LHSLo, in FloatExpandSetCCOperands()
2350 OutputChain = Tmp2->getNumValues() > 1 ? Tmp2.getValue(1) : SDValue(); in FloatExpandSetCCOperands()
2351 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
2356 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), LHSHi, in FloatExpandSetCCOperands()
2358 OutputChain = Tmp2->getNumValues() > 1 ? Tmp2.getValue(1) : SDValue(); in FloatExpandSetCCOperands()
2359 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp123 Value *Tmp2 = Builder.CreateXor(Tmp, Dividend); in generateSignedDivisionCode() local
124 Value *U_Dvnd = Builder.CreateSub(Tmp2, Tmp); in generateSignedDivisionCode()
252 Value *Tmp2 = Builder.CreateSub(MSB, SR); in generateUnsignedDivisionCode() local
253 Value *Q = Builder.CreateShl(Dividend, Tmp2); in generateUnsignedDivisionCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4256 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchBEXTRFromAndImm() local
4257 if (tryFoldLoad(Node, N0.getNode(), Input, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in matchBEXTRFromAndImm()
4259 Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Control, Input.getOperand(0)}; in matchBEXTRFromAndImm()
4293 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPISTR() local
4294 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPISTR()
4295 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPISTR()
4326 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPESTR() local
4327 if (MayFoldLoad && tryFoldLoad(Node, N2, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPESTR()
4328 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPESTR()
4619 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchVPTERNLOG() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2016 Register Tmp2 = MRI.createVirtualRegister(RC); in prepareMBB() local
2028 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareMBB()
2033 .addReg(Tmp2, getKillRegState(true)) in prepareMBB()
2044 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareMBB()
2048 .addReg(Tmp2, getKillRegState(true)) in prepareMBB()
2080 Register Tmp2 = MRI.createVirtualRegister(RC); in prepareSymbol() local
2089 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
2094 .addReg(Tmp2, getKillRegState(true)) in prepareSymbol()
2098 Register Tmp2 = MRI.createVirtualRegister(RC); in prepareSymbol() local
2109 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
[all …]
/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/
H A DExprEngineC.cpp50 ExplodedNodeSet Tmp2; in VisitBinaryOperator() local
75 evalStore(Tmp2, B, LHS, *it, state->BindExpr(B, LCtx, ExprVal), in VisitBinaryOperator()
81 StmtNodeBuilder Bldr(*it, Tmp2, *currBldrCtx); in VisitBinaryOperator()
189 evalStore(Tmp2, B, LHS, N, state, location, LHSVal); in VisitBinaryOperator()
194 getCheckerManager().runCheckersForPostStmt(Dst, Tmp2, B, *this); in VisitBinaryOperator()
H A DCheckerManager.cpp110 ExplodedNodeSet Tmp1, Tmp2; in expandGraphWithCheckers() local
118 CurrSet = (PrevSet == &Tmp1) ? &Tmp2 : &Tmp1; in expandGraphWithCheckers()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DGISelValueTracking.cpp1953 unsigned Tmp2 = in computeNumSignBits() local
1955 FirstAnswer = std::min(FirstAnswer, Tmp2); in computeNumSignBits()
1976 unsigned Tmp2 = computeNumSignBits(MO.getReg(), DemandedSub, Depth + 1); in computeNumSignBits() local
1978 FirstAnswer = std::min(FirstAnswer, Tmp2); in computeNumSignBits()
2002 unsigned Tmp2 = in computeNumSignBits() local
2004 FirstAnswer = std::min(FirstAnswer, Tmp2); in computeNumSignBits()
H A DLegalizerHelper.cpp9159 MachineInstrBuilder Tmp2; in lowerBitreverse() local
9162 Tmp2 = MIRBuilder.buildShl(SrcTy, Src, ShAmt); in lowerBitreverse()
9165 Tmp2 = MIRBuilder.buildLShr(SrcTy, Src, ShAmt); in lowerBitreverse()
9169 Tmp2 = MIRBuilder.buildAnd(SrcTy, Tmp2, Mask); in lowerBitreverse()
9171 Tmp = Tmp2; in lowerBitreverse()
9173 Tmp = MIRBuilder.buildOr(SrcTy, Tmp, Tmp2); in lowerBitreverse()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp1979 SmallVector<MachineOperand,1> Tmp2; in createPreheaderForLoop() local
1986 Tmp2.clear(); in createPreheaderForLoop()
1987 bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp2, false); in createPreheaderForLoop()
1990 if (TB != Header && (Tmp2.empty() || FB != Header)) in createPreheaderForLoop()
1999 bool LatchNotAnalyzed = TII->analyzeBranch(*Latch, TB, FB, Tmp2, false); in createPreheaderForLoop()
H A DHexagonSplitDouble.cpp683 auto *Tmp2 = in splitMemRef() local
685 HighI->addMemOperand(MF, Tmp2); in splitMemRef()
H A DHexagonISelLoweringHVX.cpp2502 SDValue Tmp2 = DAG.getNode(ShRight, dl, IntTy, Tmp0, AmtM1); in emitHvxShiftRightRnd() local
2503 SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, IntTy, Tmp2, Rup); in emitHvxShiftRightRnd()
2505 SDValue Eq = DAG.getSetCC(dl, PredTy, Tmp1, Tmp2, ISD::SETEQ); in emitHvxShiftRightRnd()
2507 SDValue Tmp4 = DAG.getNode(ShRight, dl, IntTy, {Tmp2, One}); in emitHvxShiftRightRnd()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DValueTracking.cpp4028 unsigned Tmp, Tmp2; in ComputeNumSignBitsImpl() local
4151 Tmp2 = ShAmt->getZExtValue(); in ComputeNumSignBitsImpl()
4152 return Tmp - Tmp2; in ComputeNumSignBitsImpl()
4162 Tmp2 = ComputeNumSignBits(U->getOperand(1), DemandedElts, Q, Depth + 1); in ComputeNumSignBitsImpl()
4163 FirstAnswer = std::min(Tmp, Tmp2); in ComputeNumSignBitsImpl()
4181 Tmp2 = ComputeNumSignBits(U->getOperand(2), DemandedElts, Q, Depth + 1); in ComputeNumSignBitsImpl()
4182 return std::min(Tmp, Tmp2); in ComputeNumSignBitsImpl()
4208 Tmp2 = ComputeNumSignBits(U->getOperand(1), DemandedElts, Q, Depth + 1); in ComputeNumSignBitsImpl()
4209 if (Tmp2 == 1) in ComputeNumSignBitsImpl()
4211 return std::min(Tmp, Tmp2) - 1; in ComputeNumSignBitsImpl()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2295 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); in LowerShiftRightParts() local
2296 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftRightParts()
2355 SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); in LowerShiftLeftParts() local
2356 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftLeftParts()
3055 SDValue Tmp2 = Node->getOperand(1); in LowerVAARG() local
3059 Tmp1, Tmp2, MachinePointerInfo(V)); in LowerVAARG()
3078 Tmp1 = DAG.getStore(VAListLoad.getValue(1), DL, Tmp1, Tmp2, in LowerVAARG()
3275 SDValue Tmp2 = ST->getBasePtr(); in LowerSTOREi1() local
3280 DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), MVT::i8, in LowerSTOREi1()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp2502 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); in LowerFTRUNC() local
2504 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2); in LowerFTRUNC()
2521 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFROUNDEVEN() local
2532 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2); in LowerFROUNDEVEN()
6059 unsigned Tmp2 = DAG.ComputeNumSignBits(Op.getOperand(2), Depth + 1); in ComputeNumSignBitsForTargetNode() local
6060 if (Tmp2 == 1) in ComputeNumSignBitsForTargetNode()
6071 return std::min({Tmp0, Tmp1, Tmp2}); in ComputeNumSignBitsForTargetNode()
6098 unsigned Tmp2 = Analysis.computeNumSignBits(Src2, DemandedElts, Depth + 1); in computeNumSignBitsForTargetInstr() local
6099 if (Tmp2 == 1) in computeNumSignBitsForTargetInstr()
6107 return std::min({Tmp0, Tmp1, Tmp2}); in computeNumSignBitsForTargetInstr()
H A DAMDGPULegalizerInfo.cpp2486 auto Tmp2 = B.buildFSub(Ty, Tmp1, CopySign); in legalizeFroundeven() local
2492 B.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2); in legalizeFroundeven()
4926 auto Tmp2 = B.buildFMA(ResTy, NegY, Ret, X); in legalizeFastUnsafeFDIV64() local
4928 B.buildFMA(Res, Tmp2, R, Ret); in legalizeFastUnsafeFDIV64()
H A DSIInstrInfo.cpp727 Register Tmp2 = RS.scavengeRegisterBackwards(AMDGPU::VGPR_32RegClass, MI, in indirectCopyToAGPR() local
730 if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs) in indirectCopyToAGPR()
732 Tmp = Tmp2; in indirectCopyToAGPR()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGExprComplex.cpp1092 llvm::Value *Tmp2 = Builder.CreateMul(LHSi, RHSi); // b*d in EmitBinDiv() local
1093 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd in EmitBinDiv()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp6283 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
6285 SDValue(Tmp2, 0))); in Select()
6297 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
6299 SDValue(Tmp2, 0))); in Select()
H A DPPCISelLowering.cpp9263 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); in LowerSHL_PARTS() local
9265 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); in LowerSHL_PARTS()
9292 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); in LowerSRL_PARTS() local
9294 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRL_PARTS()
9320 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); in LowerSRA_PARTS() local
9322 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRA_PARTS()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp4176 SDValue Tmp2 = CurDAG->getTargetConstant(CC, dl, MVT::i32); in Select() local
4178 SDValue Ops[] = {N1, Tmp2, CurDAG->getRegister(ARM::CPSR, MVT::i32), Chain, in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp8047 SDValue Tmp2 = Op.getOperand(1); in LowerOperation() local
8057 DAG.getNode(ISD::SETCC, DL, CCVT, Tmp1, Tmp2, CC, Op->getFlags()); in LowerOperation()
12753 SDValue Tmp2 = DAG.getNode(ISD::STRICT_FSETCCS, DL, VTList, Chain, Op2, in lowerVectorStrictFSetcc() local
12756 Tmp1.getValue(1), Tmp2.getValue(1)); in lowerVectorStrictFSetcc()
12758 if (Tmp1 != Tmp2) in lowerVectorStrictFSetcc()
12759 Tmp1 = DAG.getNode(ISD::AND, DL, VT, Tmp1, Tmp2); in lowerVectorStrictFSetcc()
21089 unsigned Tmp2 = in ComputeNumSignBitsForTargetNode() local
21091 return std::min(Tmp, Tmp2); in ComputeNumSignBitsForTargetNode()

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