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Searched refs:Tmp1 (Results 1 – 25 of 28) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp1738 SDValue Tmp1 = SDValue(Node, 0); in ExpandDYNAMIC_STACKALLOC() local
1741 SDValue Chain = Tmp1.getOperand(0); in ExpandDYNAMIC_STACKALLOC()
1757 Tmp1 = DAG.getNode(Opc, dl, VT, SP, Size); // Value in ExpandDYNAMIC_STACKALLOC()
1759 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1, in ExpandDYNAMIC_STACKALLOC()
1761 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain in ExpandDYNAMIC_STACKALLOC()
1765 Results.push_back(Tmp1); in ExpandDYNAMIC_STACKALLOC()
2795 SDValue Tmp1; in ExpandLegalINT_TO_FP() local
2797 Tmp1 = DAG.getNode(ISD::STRICT_SINT_TO_FP, dl, { DestVT, MVT::Other }, in ExpandLegalINT_TO_FP()
2800 Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2849 { Tmp1.getValue(1), Tmp1, FudgeInReg }); in ExpandLegalINT_TO_FP()
[all …]
H A DLegalizeFloatTypes.cpp2128 SDValue Tmp1, Tmp2, Tmp3, OutputChain; in FloatExpandSetCCOperands() local
2129 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), LHSHi, in FloatExpandSetCCOperands()
2131 OutputChain = Tmp1->getNumValues() > 1 ? Tmp1.getValue(1) : SDValue(); in FloatExpandSetCCOperands()
2135 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
2136 Tmp1 = in FloatExpandSetCCOperands()
2139 OutputChain = Tmp1->getNumValues() > 1 ? Tmp1.getValue(1) : SDValue(); in FloatExpandSetCCOperands()
2143 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
2144 NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3); in FloatExpandSetCCOperands()
H A DTargetLowering.cpp8139 SDValue Tmp1 = IsSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, in expandShiftParts() local
8162 Lo = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp1, Tmp3); in expandShiftParts()
8165 Hi = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp1, Tmp3); in expandShiftParts()
8930 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5; in expandVPCTPOP() local
8933 Tmp1 = DAG.getNode(ISD::VP_AND, dl, VT, in expandVPCTPOP()
8937 Op = DAG.getNode(ISD::VP_SUB, dl, VT, Op, Tmp1, Mask, VL); in expandVPCTPOP()
9370 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; in expandBSWAP() local
9384 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); in expandBSWAP()
9386 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); in expandBSWAP()
9408 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT)); in expandBSWAP()
[all …]
H A DSelectionDAG.cpp2419 SDValue Tmp1 = Node->getOperand(0); in expandVAArg() local
2423 SDValue VAListLoad = getLoad(TLI.getPointerTy(getDataLayout()), dl, Tmp1, in expandVAArg()
2437 Tmp1 = getNode(ISD::ADD, dl, VAList.getValueType(), VAList, in expandVAArg()
2442 Tmp1 = in expandVAArg()
2443 getStore(VAListLoad.getValue(1), dl, Tmp1, Tmp2, MachinePointerInfo(V)); in expandVAArg()
2445 return getLoad(VT, dl, Tmp1, VAList, MachinePointerInfo()); in expandVAArg()
2455 SDValue Tmp1 = in expandVACopy() local
2458 return getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), in expandVACopy()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DIntrinsicLowering.cpp63 Value *Tmp1 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
67 V = Builder.CreateOr(Tmp1, Tmp2, "bswap.i16"); in LowerBSWAP()
77 Value *Tmp1 = Builder.CreateLShr(V,ConstantInt::get(V->getType(), 24), in LowerBSWAP() local
86 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or2"); in LowerBSWAP()
107 Value* Tmp1 = Builder.CreateLShr(V, in LowerBSWAP() local
137 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or4"); in LowerBSWAP()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp122 Value *Tmp1 = Builder.CreateAShr(Divisor, Shift); in generateSignedDivisionCode() local
125 Value *Tmp3 = Builder.CreateXor(Tmp1, Divisor); in generateSignedDivisionCode()
126 Value *U_Dvsr = Builder.CreateSub(Tmp3, Tmp1); in generateSignedDivisionCode()
127 Value *Q_Sgn = Builder.CreateXor(Tmp1, Tmp); in generateSignedDivisionCode()
235 Value *Tmp1 = Builder.CreateCall(CTLZ, {Dividend, True}); in generateUnsignedDivisionCode() local
236 Value *SR = Builder.CreateSub(Tmp0, Tmp1); in generateUnsignedDivisionCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2029 Register Tmp1 = MRI.createVirtualRegister(RC); in prepareMBB() local
2038 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareMBB()
2043 .addReg(Tmp1, getKillRegState(true)) in prepareMBB()
2054 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareMBB()
2059 .addReg(Tmp1, getKillRegState(true)) in prepareMBB()
2093 Register Tmp1 = MRI.createVirtualRegister(RC); in prepareSymbol() local
2099 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
2104 .addReg(Tmp1, getKillRegState(true)) in prepareSymbol()
2111 Register Tmp1 = MRI.createVirtualRegister(RC); in prepareSymbol() local
2119 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4190 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchBEXTRFromAndImm() local
4191 if (tryFoldLoad(Node, N0.getNode(), Input, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in matchBEXTRFromAndImm()
4193 Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Control, Input.getOperand(0)}; in matchBEXTRFromAndImm()
4227 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPISTR() local
4228 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPISTR()
4229 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPISTR()
4260 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPESTR() local
4261 if (MayFoldLoad && tryFoldLoad(Node, N2, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPESTR()
4262 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPESTR()
4553 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchVPTERNLOG() local
[all …]
/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/
H A DCheckerManager.cpp123 ExplodedNodeSet Tmp1, Tmp2; in expandGraphWithCheckers() local
131 CurrSet = (PrevSet == &Tmp1) ? &Tmp2 : &Tmp1; in expandGraphWithCheckers()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp503 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
505 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); in LowerFPToInt()
519 BuildMI(BB, DL, TII.get(FConst), Tmp1) in LowerFPToInt()
521 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
525 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); in LowerFPToInt()
529 BuildMI(BB, DL, TII.get(FConst), Tmp1) in LowerFPToInt()
531 BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp1859 SmallVector<MachineOperand,2> Tmp1; in createPreheaderForLoop() local
1862 if (TII->analyzeBranch(*ExitingBlock, TB, FB, Tmp1, false)) in createPreheaderForLoop()
1866 bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp1, false); in createPreheaderForLoop()
H A DHexagonSplitDouble.cpp687 auto *Tmp1 = MF.getMachineMemOperand(Ptr, F, 4 /*size*/, A); in splitMemRef() local
688 LowI->addMemOperand(MF, Tmp1); in splitMemRef()
H A DHexagonISelLoweringHVX.cpp2464 SDValue Tmp1 = DAG.getNode(ShRight, dl, IntTy, Inp, AmtM1); in emitHvxShiftRightRnd()
2468 SDValue Eq = DAG.getSetCC(dl, PredTy, Tmp1, Tmp2, ISD::SETEQ); in emitHvxShiftRightRnd()
2465 SDValue Tmp1 = DAG.getNode(ShRight, dl, IntTy, Inp, AmtM1); emitHvxShiftRightRnd() local
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2463 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); in LowerShiftRightParts() local
2467 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftRightParts()
2523 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); in LowerShiftLeftParts() local
2527 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftLeftParts()
2829 SDValue Tmp1 = Node->getOperand(0); in LowerVAARG() local
2834 Tmp1, Tmp2, MachinePointerInfo(V)); in LowerVAARG()
2848 Tmp1 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, in LowerVAARG()
2853 Tmp1 = DAG.getStore(VAListLoad.getValue(1), DL, Tmp1, Tmp2, in LowerVAARG()
2860 return DAG.getLoad(VT, DL, Tmp1, VAList, MachinePointerInfo(SrcV)); in LowerVAARG()
3094 SDValue Tmp1 = ST->getChain(); in LowerSTOREi1() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPromoteAlloca.cpp1482 Value *Tmp1 = Builder.CreateMul(TIdY, TCntZ, "", true, true); in tryPromoteAllocaToLDS() local
1483 Value *TID = Builder.CreateAdd(Tmp0, Tmp1); in tryPromoteAllocaToLDS()
H A DAMDGPUISelLowering.cpp2444 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC() local
2445 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); in LowerFTRUNC()
2463 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFROUNDEVEN() local
2464 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFROUNDEVEN()
5840 unsigned Tmp1 = DAG.ComputeNumSignBits(Op.getOperand(1), Depth + 1); in ComputeNumSignBitsForTargetNode() local
5841 if (Tmp1 == 1) in ComputeNumSignBitsForTargetNode()
5848 return std::min({Tmp0, Tmp1, Tmp2}); in ComputeNumSignBitsForTargetNode()
5879 unsigned Tmp1 = Analysis.computeNumSignBits(Src1, DemandedElts, Depth + 1); in computeNumSignBitsForTargetInstr() local
5880 if (Tmp1 == 1) in computeNumSignBitsForTargetInstr()
5885 return std::min({Tmp0, Tmp1, Tmp2}); in computeNumSignBitsForTargetInstr()
H A DAMDGPULegalizerInfo.cpp2435 auto Tmp1 = B.buildFAdd(Ty, Src, CopySign); in legalizeFroundeven() local
2436 auto Tmp2 = B.buildFSub(Ty, Tmp1, CopySign); in legalizeFroundeven()
2549 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0); in legalizeIntrinsicTrunc() local
2550 B.buildSelect(MI.getOperand(0).getReg(), ExpGt51, Src, Tmp1); in legalizeIntrinsicTrunc()
4864 auto Tmp1 = B.buildFMA(ResTy, NegY, R, One); in legalizeFastUnsafeFDIV64() local
4865 R = B.buildFMA(ResTy, Tmp1, R, R); in legalizeFastUnsafeFDIV64()
H A DSIISelLowering.cpp3966 SDValue Tmp1 = Op; in lowerDYNAMIC_STACKALLOCImpl() local
3969 SDValue Chain = Tmp1.getOperand(0); in lowerDYNAMIC_STACKALLOCImpl()
3991 Tmp1 = DAG.getNode(Opc, dl, VT, SP, ScaledSize); // Value in lowerDYNAMIC_STACKALLOCImpl()
3993 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1, in lowerDYNAMIC_STACKALLOCImpl()
3999 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain in lowerDYNAMIC_STACKALLOCImpl()
4002 return DAG.getMergeValues({Tmp1, Tmp2}, dl); in lowerDYNAMIC_STACKALLOCImpl()
10517 SDValue Tmp1 = DAG.getNode(ISD::FMA, SL, VT, NegY, R, One); in lowerFastUnsafeFDIV64() local
10518 R = DAG.getNode(ISD::FMA, SL, VT, Tmp1, R, R); in lowerFastUnsafeFDIV64()
/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DAPInt.cpp722 uint64_t Tmp1 = llvm::byteswap<uint64_t>(U.VAL); in byteSwap() local
723 Tmp1 >>= (64 - BitWidth); in byteSwap()
724 return APInt(BitWidth, Tmp1); in byteSwap()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGExprComplex.cpp1091 llvm::Value *Tmp1 = Builder.CreateMul(LHSr, RHSr); // a*c in EmitBinDiv() local
1093 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd in EmitBinDiv()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6040 SDValue Tmp1 = Op.getOperand(1); in LowerFCOPYSIGN() local
6043 EVT SrcVT = Tmp1.getValueType(); in LowerFCOPYSIGN()
6061 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); in LowerFCOPYSIGN()
6063 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN()
6064 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), in LowerFCOPYSIGN()
6067 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64, in LowerFCOPYSIGN()
6068 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), in LowerFCOPYSIGN()
6071 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); in LowerFCOPYSIGN()
6080 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask), in LowerFCOPYSIGN()
6095 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp6268 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
6271 ReplaceNode(N, CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0), in Select()
6282 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
6285 ReplaceNode(N, CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0), in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp3196 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); in LowerUMULO_SMULO() local
3197 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); in LowerUMULO_SMULO()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp2882 SDValue Tmp1, Tmp2; in ReplaceNodeResults() local
2883 TLI.expandFP_TO_UINT(N, Tmp1, Tmp2, DAG); in ReplaceNodeResults()
2884 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Tmp1)); in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp6928 SDValue Tmp1 = Op.getOperand(0); in LowerOperation() local
6934 EVT CmpVT = Tmp1.getValueType(); in LowerOperation()
6939 DAG.getNode(ISD::SETCC, DL, CCVT, Tmp1, Tmp2, CC, Op->getFlags()); in LowerOperation()
11030 SDValue Tmp1 = DAG.getNode(ISD::STRICT_FSETCCS, DL, VTList, Chain, Op1, in lowerVectorStrictFSetcc() local
11035 Tmp1.getValue(1), Tmp2.getValue(1)); in lowerVectorStrictFSetcc()
11037 if (Tmp1 != Tmp2) in lowerVectorStrictFSetcc()
11038 Tmp1 = DAG.getNode(ISD::AND, DL, VT, Tmp1, Tmp2); in lowerVectorStrictFSetcc()
11039 return DAG.getMergeValues({Tmp1, OutChain}, DL); in lowerVectorStrictFSetcc()

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