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Searched refs:Tmp1 (Results 1 – 25 of 29) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp1802 SDValue Tmp1 = SDValue(Node, 0); in ExpandDYNAMIC_STACKALLOC() local
1805 SDValue Chain = Tmp1.getOperand(0); in ExpandDYNAMIC_STACKALLOC()
1821 Tmp1 = DAG.getNode(Opc, dl, VT, SP, Size); // Value in ExpandDYNAMIC_STACKALLOC()
1823 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1, in ExpandDYNAMIC_STACKALLOC()
1825 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain in ExpandDYNAMIC_STACKALLOC()
1829 Results.push_back(Tmp1); in ExpandDYNAMIC_STACKALLOC()
2822 SDValue Tmp1; in ExpandLegalINT_TO_FP() local
2824 Tmp1 = DAG.getNode(ISD::STRICT_SINT_TO_FP, dl, { DestVT, MVT::Other }, in ExpandLegalINT_TO_FP()
2827 Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2876 { Tmp1.getValue(1), Tmp1, FudgeInReg }); in ExpandLegalINT_TO_FP()
[all …]
H A DLegalizeFloatTypes.cpp2344 SDValue Tmp1, Tmp2, Tmp3, OutputChain; in FloatExpandSetCCOperands() local
2345 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), LHSHi, in FloatExpandSetCCOperands()
2347 OutputChain = Tmp1->getNumValues() > 1 ? Tmp1.getValue(1) : SDValue(); in FloatExpandSetCCOperands()
2351 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
2352 Tmp1 = in FloatExpandSetCCOperands()
2355 OutputChain = Tmp1->getNumValues() > 1 ? Tmp1.getValue(1) : SDValue(); in FloatExpandSetCCOperands()
2359 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
2360 NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3); in FloatExpandSetCCOperands()
H A DTargetLowering.cpp8357 SDValue Tmp1 = IsSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, in expandShiftParts() local
8380 Lo = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp1, Tmp3); in expandShiftParts()
8383 Hi = DAG.getNode(ISD::SELECT, dl, VT, Cond, Tmp1, Tmp3); in expandShiftParts()
9335 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5; in expandVPCTPOP() local
9338 Tmp1 = DAG.getNode(ISD::VP_AND, dl, VT, in expandVPCTPOP()
9342 Op = DAG.getNode(ISD::VP_SUB, dl, VT, Op, Tmp1, Mask, VL); in expandVPCTPOP()
9865 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; in expandBSWAP() local
9879 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); in expandBSWAP()
9881 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); in expandBSWAP()
9903 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT)); in expandBSWAP()
[all …]
H A DSelectionDAG.cpp2657 SDValue Tmp1 = Node->getOperand(0); in expandVAArg() local
2661 SDValue VAListLoad = getLoad(TLI.getPointerTy(getDataLayout()), dl, Tmp1, in expandVAArg()
2675 Tmp1 = getNode(ISD::ADD, dl, VAList.getValueType(), VAList, in expandVAArg()
2680 Tmp1 = in expandVAArg()
2681 getStore(VAListLoad.getValue(1), dl, Tmp1, Tmp2, MachinePointerInfo(V)); in expandVAArg()
2683 return getLoad(VT, dl, Tmp1, VAList, MachinePointerInfo()); in expandVAArg()
2693 SDValue Tmp1 = in expandVACopy() local
2696 return getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), in expandVACopy()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DIntrinsicLowering.cpp63 Value *Tmp1 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
67 V = Builder.CreateOr(Tmp1, Tmp2, "bswap.i16"); in LowerBSWAP()
77 Value *Tmp1 = Builder.CreateLShr(V,ConstantInt::get(V->getType(), 24), in LowerBSWAP() local
86 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or2"); in LowerBSWAP()
107 Value* Tmp1 = Builder.CreateLShr(V, in LowerBSWAP() local
137 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or4"); in LowerBSWAP()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp122 Value *Tmp1 = Builder.CreateAShr(Divisor, Shift); in generateSignedDivisionCode() local
125 Value *Tmp3 = Builder.CreateXor(Tmp1, Divisor); in generateSignedDivisionCode()
126 Value *U_Dvsr = Builder.CreateSub(Tmp3, Tmp1); in generateSignedDivisionCode()
127 Value *Q_Sgn = Builder.CreateXor(Tmp1, Tmp); in generateSignedDivisionCode()
235 Value *Tmp1 = Builder.CreateCall(CTLZ, {Dividend, True}); in generateUnsignedDivisionCode() local
236 Value *SR = Builder.CreateSub(Tmp0, Tmp1); in generateUnsignedDivisionCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2015 Register Tmp1 = MRI.createVirtualRegister(RC); in prepareMBB() local
2024 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareMBB()
2029 .addReg(Tmp1, getKillRegState(true)) in prepareMBB()
2040 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareMBB()
2045 .addReg(Tmp1, getKillRegState(true)) in prepareMBB()
2079 Register Tmp1 = MRI.createVirtualRegister(RC); in prepareSymbol() local
2085 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
2090 .addReg(Tmp1, getKillRegState(true)) in prepareSymbol()
2097 Register Tmp1 = MRI.createVirtualRegister(RC); in prepareSymbol() local
2105 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4256 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchBEXTRFromAndImm() local
4257 if (tryFoldLoad(Node, N0.getNode(), Input, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in matchBEXTRFromAndImm()
4259 Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Control, Input.getOperand(0)}; in matchBEXTRFromAndImm()
4293 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPISTR() local
4294 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPISTR()
4295 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPISTR()
4326 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPESTR() local
4327 if (MayFoldLoad && tryFoldLoad(Node, N2, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { in emitPCMPESTR()
4328 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm, in emitPCMPESTR()
4619 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchVPTERNLOG() local
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/freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/
H A DCheckerManager.cpp110 ExplodedNodeSet Tmp1, Tmp2; in expandGraphWithCheckers() local
118 CurrSet = (PrevSet == &Tmp1) ? &Tmp2 : &Tmp1; in expandGraphWithCheckers()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2292 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); in LowerShiftRightParts() local
2296 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftRightParts()
2352 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); in LowerShiftLeftParts() local
2356 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); in LowerShiftLeftParts()
2487 SDValue Tmp1 = DAG.getFPExtendOrRound(N->getOperand(1), DL, NVT); in PromoteBinOpToF32() local
2488 SDValue Res = DAG.getNode(N->getOpcode(), DL, NVT, Tmp0, Tmp1, N->getFlags()); in PromoteBinOpToF32()
3054 SDValue Tmp1 = Node->getOperand(0); in LowerVAARG() local
3059 Tmp1, Tmp2, MachinePointerInfo(V)); in LowerVAARG()
3073 Tmp1 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, in LowerVAARG()
3078 Tmp1 = DAG.getStore(VAListLoad.getValue(1), DL, Tmp1, Tmp2, in LowerVAARG()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp1896 SmallVector<MachineOperand,2> Tmp1; in createPreheaderForLoop() local
1899 if (TII->analyzeBranch(*ExitingBlock, TB, FB, Tmp1, false)) in createPreheaderForLoop()
1903 bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp1, false); in createPreheaderForLoop()
H A DHexagonSplitDouble.cpp681 auto *Tmp1 = MF.getMachineMemOperand(Ptr, F, 4 /*size*/, A); in splitMemRef() local
682 LowI->addMemOperand(MF, Tmp1); in splitMemRef()
H A DHexagonISelLoweringHVX.cpp2501 SDValue Tmp1 = DAG.getNode(ShRight, dl, IntTy, Inp, AmtM1); in emitHvxShiftRightRnd() local
2505 SDValue Eq = DAG.getSetCC(dl, PredTy, Tmp1, Tmp2, ISD::SETEQ); in emitHvxShiftRightRnd()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp550 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
552 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); in LowerFPToInt()
566 BuildMI(BB, DL, TII.get(FConst), Tmp1) in LowerFPToInt()
568 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
572 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); in LowerFPToInt()
576 BuildMI(BB, DL, TII.get(FConst), Tmp1) in LowerFPToInt()
578 BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPromoteAlloca.cpp1561 Value *Tmp1 = Builder.CreateMul(TIdY, TCntZ, "", true, true); in tryPromoteAllocaToLDS() local
1562 Value *TID = Builder.CreateAdd(Tmp0, Tmp1); in tryPromoteAllocaToLDS()
H A DAMDGPUISelLowering.cpp2501 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC() local
2502 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); in LowerFTRUNC()
2520 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFROUNDEVEN() local
2521 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFROUNDEVEN()
6063 unsigned Tmp1 = DAG.ComputeNumSignBits(Op.getOperand(1), Depth + 1); in ComputeNumSignBitsForTargetNode() local
6064 if (Tmp1 == 1) in ComputeNumSignBitsForTargetNode()
6071 return std::min({Tmp0, Tmp1, Tmp2}); in ComputeNumSignBitsForTargetNode()
6101 unsigned Tmp1 = Analysis.computeNumSignBits(Src1, DemandedElts, Depth + 1); in computeNumSignBitsForTargetInstr() local
6102 if (Tmp1 == 1) in computeNumSignBitsForTargetInstr()
6107 return std::min({Tmp0, Tmp1, Tmp2}); in computeNumSignBitsForTargetInstr()
H A DAMDGPULegalizerInfo.cpp2485 auto Tmp1 = B.buildFAdd(Ty, Src, CopySign); in legalizeFroundeven() local
2486 auto Tmp2 = B.buildFSub(Ty, Tmp1, CopySign); in legalizeFroundeven()
2599 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0); in legalizeIntrinsicTrunc() local
2600 B.buildSelect(MI.getOperand(0).getReg(), ExpGt51, Src, Tmp1); in legalizeIntrinsicTrunc()
4922 auto Tmp1 = B.buildFMA(ResTy, NegY, R, One); in legalizeFastUnsafeFDIV64() local
4923 R = B.buildFMA(ResTy, Tmp1, R, R); in legalizeFastUnsafeFDIV64()
H A DAMDGPURegisterBankInfo.cpp1213 auto Tmp1 = B.buildPtrAdd(PtrTy, OldSP, in applyMappingDynStackAlloc() local
1215 B.buildMaskLowPtrBits(Dst, Tmp1, in applyMappingDynStackAlloc()
/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DAPInt.cpp753 uint64_t Tmp1 = llvm::byteswap<uint64_t>(U.VAL); in byteSwap() local
754 Tmp1 >>= (64 - BitWidth); in byteSwap()
755 return APInt(BitWidth, Tmp1); in byteSwap()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGExprComplex.cpp1091 llvm::Value *Tmp1 = Builder.CreateMul(LHSr, RHSr); // a*c in EmitBinDiv() local
1093 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd in EmitBinDiv()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6113 SDValue Tmp1 = Op.getOperand(1); in LowerFCOPYSIGN() local
6116 EVT SrcVT = Tmp1.getValueType(); in LowerFCOPYSIGN()
6134 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); in LowerFCOPYSIGN()
6136 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT, in LowerFCOPYSIGN()
6137 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), in LowerFCOPYSIGN()
6140 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64, in LowerFCOPYSIGN()
6141 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), in LowerFCOPYSIGN()
6144 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); in LowerFCOPYSIGN()
6153 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask), in LowerFCOPYSIGN()
6168 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp6281 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
6284 ReplaceNode(N, CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0), in Select()
6295 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); in Select() local
6298 ReplaceNode(N, CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0), in Select()
H A DPPCISelLowering.cpp9261 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, in LowerSHL_PARTS() local
9264 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); in LowerSHL_PARTS()
9290 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, in LowerSRL_PARTS() local
9293 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRL_PARTS()
9318 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, in LowerSRA_PARTS() local
9321 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRA_PARTS()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp8046 SDValue Tmp1 = Op.getOperand(0); in LowerOperation() local
8052 EVT CmpVT = Tmp1.getValueType(); in LowerOperation()
8057 DAG.getNode(ISD::SETCC, DL, CCVT, Tmp1, Tmp2, CC, Op->getFlags()); in LowerOperation()
12751 SDValue Tmp1 = DAG.getNode(ISD::STRICT_FSETCCS, DL, VTList, Chain, Op1, in lowerVectorStrictFSetcc() local
12756 Tmp1.getValue(1), Tmp2.getValue(1)); in lowerVectorStrictFSetcc()
12758 if (Tmp1 != Tmp2) in lowerVectorStrictFSetcc()
12759 Tmp1 = DAG.getNode(ISD::AND, DL, VT, Tmp1, Tmp2); in lowerVectorStrictFSetcc()
12760 return DAG.getMergeValues({Tmp1, OutChain}, DL); in lowerVectorStrictFSetcc()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp4103 SDValue Tmp1, Tmp2; in ReplaceNodeResults() local
4104 TLI.expandFP_TO_UINT(N, Tmp1, Tmp2, DAG); in ReplaceNodeResults()
4105 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Tmp1)); in ReplaceNodeResults()

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