Lines Matching refs:Tmp1

2029   Register Tmp1 = MRI.createVirtualRegister(RC);  in prepareMBB()  local
2038 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareMBB()
2043 .addReg(Tmp1, getKillRegState(true)) in prepareMBB()
2054 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareMBB()
2059 .addReg(Tmp1, getKillRegState(true)) in prepareMBB()
2093 Register Tmp1 = MRI.createVirtualRegister(RC); in prepareSymbol() local
2099 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
2104 .addReg(Tmp1, getKillRegState(true)) in prepareSymbol()
2111 Register Tmp1 = MRI.createVirtualRegister(RC); in prepareSymbol() local
2119 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
2124 .addReg(Tmp1, getKillRegState(true)) in prepareSymbol()
2136 Register Tmp1 = MRI.createVirtualRegister(RC); in prepareSymbol() local
2142 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
2147 .addReg(Tmp1, getKillRegState(true)) in prepareSymbol()
2522 Register Tmp1 = MRI.createVirtualRegister(RC); in emitSjLjDispatchBlock() local
2530 BuildMI(DispContBB, DL, TII->get(VE::LEAzii), Tmp1) in emitSjLjDispatchBlock()
2535 .addReg(Tmp1, getKillRegState(true)) in emitSjLjDispatchBlock()
2546 BuildMI(DispContBB, DL, TII->get(VE::LEAzii), Tmp1) in emitSjLjDispatchBlock()
2551 .addReg(Tmp1, getKillRegState(true)) in emitSjLjDispatchBlock()
2567 Register Tmp1 = MRI.createVirtualRegister(RC); in emitSjLjDispatchBlock() local
2569 BuildMI(DispContBB, DL, TII->get(VE::SLLri), Tmp1) in emitSjLjDispatchBlock()
2574 .addReg(Tmp1, getKillRegState(true)) in emitSjLjDispatchBlock()
2593 Register Tmp1 = MRI.createVirtualRegister(RC); in emitSjLjDispatchBlock() local
2595 BuildMI(DispContBB, DL, TII->get(VE::SLLri), Tmp1) in emitSjLjDispatchBlock()
2600 .addReg(Tmp1, getKillRegState(true)) in emitSjLjDispatchBlock()