| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 389 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass); in materializeFP() local
390 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
420 Register TempReg = createResultReg(RC); in materializeGV() local
421 emitInst(Mips::ADDiu, TempReg) in materializeGV()
424 DestReg = TempReg; in materializeGV()
646 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp() local
647 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
648 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
652 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp() local
653 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 658 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg in emitPrologue() local
690 &MBB, false, twoUniqueScratchRegsRequired(&MBB), &ScratchReg, &TempReg); in emitPrologue()
694 SingleScratchReg = ScratchReg == TempReg; in emitPrologue()
797 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFOCRF8), TempReg); in emitPrologue()
801 BuildMI(MBB, MBBI, dl, MoveFromCondRegInst, TempReg); in emitPrologue()
812 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
878 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
926 .addDef(TempReg) in emitPrologue()
957 TII.materializeImmPostRA(MBB, MBBI, dl, TempReg, NegFrameSize); in emitPrologue()
960 .addReg(TempReg, RegState::Kill); in emitPrologue()
[all …]
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| H A D | PPCISelDAGToDAG.cpp | 485 Register TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); in INITIALIZE_PASS() local
488 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg); in INITIALIZE_PASS()
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| H A D | PPCISelLowering.cpp | 13603 Register TempReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca() local
13604 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS), TempReg) in emitProbedAlloca()
13608 .addReg(TempReg) in emitProbedAlloca()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetMachine.cpp | 1807 Register TempReg; in parseMachineFunctionInfo() local
1808 if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) { in parseMachineFunctionInfo()
1812 RegVal = TempReg; in parseMachineFunctionInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1852 Register TempReg = MI.getOperand(1).getReg(); in ExpandCMP_SWAP() local
1916 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg) in ExpandCMP_SWAP()
1926 .addReg(TempReg, RegState::Kill) in ExpandCMP_SWAP()
1987 Register TempReg = TRI->getSubReg(AddrAndTempReg, ARM::gsub_1); in ExpandCMP_SWAP_64() local
2043 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg); in ExpandCMP_SWAP_64()
2050 .addReg(TempReg, RegState::Kill) in ExpandCMP_SWAP_64()
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| H A D | ARMFastISel.cpp | 3042 Register TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass); in ARMLowerPICELF() local
3045 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), TempReg) in ARMLowerPICELF()
3058 .addReg(TempReg) in ARMLowerPICELF()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 918 unsigned TempReg = AddrReg == X86::R10 ? X86::R11D : X86::R10D; in LowerKCFI_CHECK() local
920 MCInstBuilder(X86::MOV32ri).addReg(TempReg).addImm(-MaskKCFIType(Type))); in LowerKCFI_CHECK()
923 .addReg(TempReg) in LowerKCFI_CHECK()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 3746 MCRegister TempReg = Inst.getOperand(1).getReg(); in validateInstruction() local
3747 if (DestReg == TempReg) { in validateInstruction()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | GlobalISelEmitter.cpp | 406 unsigned TempReg) const;
|