| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 391 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass); in materializeFP() local
392 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
422 Register TempReg = createResultReg(RC); in materializeGV() local
423 emitInst(Mips::ADDiu, TempReg) in materializeGV()
426 DestReg = TempReg; in materializeGV()
648 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp() local
649 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
650 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
654 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp() local
655 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 658 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg in emitPrologue() local
690 &MBB, false, twoUniqueScratchRegsRequired(&MBB), &ScratchReg, &TempReg); in emitPrologue()
694 SingleScratchReg = ScratchReg == TempReg; in emitPrologue()
797 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFOCRF8), TempReg); in emitPrologue()
801 BuildMI(MBB, MBBI, dl, MoveFromCondRegInst, TempReg); in emitPrologue()
812 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
878 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
924 .addDef(TempReg) in emitPrologue()
955 TII.materializeImmPostRA(MBB, MBBI, dl, TempReg, NegFrameSize); in emitPrologue()
958 .addReg(TempReg, RegState::Kill); in emitPrologue()
[all …]
|
| H A D | PPCISelDAGToDAG.cpp | 485 Register TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); in INITIALIZE_PASS() local
488 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg); in INITIALIZE_PASS()
|
| H A D | PPCISelLowering.cpp | 12775 Register TempReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca() local
12776 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS), TempReg) in emitProbedAlloca()
12780 .addReg(TempReg) in emitProbedAlloca()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetMachine.cpp | 1553 Register TempReg; in parseMachineFunctionInfo() local
1554 if (parseNamedRegisterReference(PFS, TempReg, RegName.Value, Error)) { in parseMachineFunctionInfo()
1558 RegVal = TempReg; in parseMachineFunctionInfo()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 1815 Register TempReg = MI.getOperand(1).getReg(); in ExpandCMP_SWAP() local
1879 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg) in ExpandCMP_SWAP()
1889 .addReg(TempReg, RegState::Kill) in ExpandCMP_SWAP()
1945 Register TempReg = MI.getOperand(1).getReg(); in ExpandCMP_SWAP_64() local
2003 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg); in ExpandCMP_SWAP_64()
2010 .addReg(TempReg, RegState::Kill) in ExpandCMP_SWAP_64()
|
| H A D | ARMFastISel.cpp | 2972 Register TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass); in ARMLowerPICELF() local
2975 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), TempReg) in ARMLowerPICELF()
2988 .addReg(TempReg) in ARMLowerPICELF()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 922 unsigned TempReg = AddrReg == X86::R10 ? X86::R11D : X86::R10D; in LowerKCFI_CHECK() local
924 MCInstBuilder(X86::MOV32ri).addReg(TempReg).addImm(-MaskKCFIType(Type))); in LowerKCFI_CHECK()
927 .addReg(TempReg) in LowerKCFI_CHECK()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 3473 unsigned TempReg = Inst.getOperand(1).getReg(); in validateInstruction() local
3474 if (DestReg == TempReg) { in validateInstruction()
|
| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | GlobalISelEmitter.cpp | 403 const TreePatternNode &Src, unsigned TempReg);
|