391     unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);  in materializeFP()  local
392     emitInst(Mips::MTC1, DestReg).addReg(TempReg);  in materializeFP()
422     Register TempReg = createResultReg(RC);  in materializeGV()  local
423     emitInst(Mips::ADDiu, TempReg)  in materializeGV()
426     DestReg = TempReg;  in materializeGV()
648     Register TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()  local
649     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);  in emitCmp()
650     emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
654     Register TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()  local
655     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);  in emitCmp()
656     emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);  in emitCmp()
666     Register TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()  local
667     emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);  in emitCmp()
668     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
672     Register TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()  local
673     emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);  in emitCmp()
674     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
684     Register TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()  local
685     emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);  in emitCmp()
686     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
690     Register TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()  local
691     emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);  in emitCmp()
692     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
1053   Register TempReg = createResultReg(RC);  in selectSelect()  local
1055   if (!ResultReg || !TempReg)  in selectSelect()
1058   emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);  in selectSelect()
1060     .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);  in selectSelect()
1119   Register TempReg = createResultReg(&Mips::FGR32RegClass);  in selectFPToInt()  local
1123   emitInst(Opc, TempReg).addReg(SrcReg);  in selectFPToInt()
1124   emitInst(Mips::MFC1, DestReg).addReg(TempReg);  in selectFPToInt()
1603         unsigned TempReg[3];  in fastLowerIntrinsicCall()  local
1604         for (unsigned &R : TempReg) {  in fastLowerIntrinsicCall()
1609         emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);  in fastLowerIntrinsicCall()
1610         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);  in fastLowerIntrinsicCall()
1611         emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[1]).addImm(0xFF);  in fastLowerIntrinsicCall()
1612         emitInst(Mips::OR, DestReg).addReg(TempReg[0]).addReg(TempReg[2]);  in fastLowerIntrinsicCall()
1618         Register TempReg = createResultReg(&Mips::GPR32RegClass);  in fastLowerIntrinsicCall()  local
1619         emitInst(Mips::WSBH, TempReg).addReg(SrcReg);  in fastLowerIntrinsicCall()
1620         emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);  in fastLowerIntrinsicCall()
1624         unsigned TempReg[8];  in fastLowerIntrinsicCall()  local
1625         for (unsigned &R : TempReg) {  in fastLowerIntrinsicCall()
1631         emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);  in fastLowerIntrinsicCall()
1632         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);  in fastLowerIntrinsicCall()
1633         emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);  in fastLowerIntrinsicCall()
1634         emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);  in fastLowerIntrinsicCall()
1636         emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);  in fastLowerIntrinsicCall()
1637         emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);  in fastLowerIntrinsicCall()
1639         emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);  in fastLowerIntrinsicCall()
1640         emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);  in fastLowerIntrinsicCall()
1641         emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);  in fastLowerIntrinsicCall()
1836   Register TempReg = createResultReg(&Mips::GPR32RegClass);  in emitIntSExt32r1()  local
1837   emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);  in emitIntSExt32r1()
1838   emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);  in emitIntSExt32r1()
1971     Register TempReg = createResultReg(&Mips::GPR32RegClass);  in selectShift()  local
1972     if (!TempReg)  in selectShift()
1977     if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))  in selectShift()
1980     Op0Reg = TempReg;  in selectShift()
2097     Register TempReg = createResultReg(&Mips::GPR32RegClass);  in getRegEnsuringSimpleIntegerWidening()  local
2098     if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))  in getRegEnsuringSimpleIntegerWidening()
2100     VReg = TempReg;  in getRegEnsuringSimpleIntegerWidening()
2107     unsigned TempReg =  in simplifyAddress()  local
2110     emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());  in simplifyAddress()