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Searched refs:TSFlags (Results 1 – 25 of 145) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.h146 static inline unsigned getFormat(uint64_t TSFlags) { in getFormat() argument
147 return (TSFlags & InstFormatMask) >> InstFormatShift; in getFormat()
150 static inline RISCVVType::VLMUL getLMul(uint64_t TSFlags) { in getLMul() argument
151 return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulMask) >> VLMulShift); in getLMul()
154 static inline bool isTiedPseudo(uint64_t TSFlags) { in isTiedPseudo() argument
155 return TSFlags & IsTiedPseudoMask; in isTiedPseudo()
158 static inline bool hasSEWOp(uint64_t TSFlags) { in hasSEWOp() argument
159 return TSFlags & HasSEWOpMask; in hasSEWOp()
162 static inline bool hasVLOp(uint64_t TSFlags) { in hasVLOp() argument
163 return TSFlags & HasVLOpMask; in hasVLOp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td73 let TSFlags{6-0} = Type.Value;
77 let TSFlags{7} = isSolo;
80 let TSFlags{8} = isSoloAX;
83 let TSFlags{9} = isRestrictSlot1AOK;
87 let TSFlags{10} = isPredicated;
89 let TSFlags{11} = isPredicatedFalse;
91 let TSFlags{12} = isPredicatedNew;
93 let TSFlags{13} = isPredicateLate; // Late predicate producer insn.
97 let TSFlags{14} = isNewValue; // New-value consumer insn.
99 let TSFlags{15} = hasNewValue; // New-value producer insn.
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrFormats.td163 let TSFlags{0} = SALU;
164 let TSFlags{1} = VALU;
166 let TSFlags{2} = SOP1;
167 let TSFlags{3} = SOP2;
168 let TSFlags{4} = SOPC;
169 let TSFlags{5} = SOPK;
170 let TSFlags{6} = SOPP;
172 let TSFlags{7} = VOP1;
173 let TSFlags{8} = VOP2;
174 let TSFlags{9} = VOPC;
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H A DSIInstrInfo.h428 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
432 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
436 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
440 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
460 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
464 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
468 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
472 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
476 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
480 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
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H A DR600InstrFormats.td53 let TSFlags{4} = Trig;
54 let TSFlags{5} = Op3;
58 let TSFlags{6} = isVector;
59 let TSFlags{8-7} = FlagOperandIdx;
60 let TSFlags{9} = HasNativeOperands;
61 let TSFlags{10} = Op1;
62 let TSFlags{11} = Op2;
63 let TSFlags{12} = VTXInst;
64 let TSFlags{13} = TEXInst;
65 let TSFlags{14} = ALUInst;
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H A DAMDGPUInsertDelayAlu.cpp39 if (MI.getDesc().TSFlags & VA_VDST_0) in instructionWaitsForVALU()
52 uint64_t MIFlags = MI.getDesc().TSFlags; in instructionWaitsForSGPRWrites()
69 static DelayType getDelayType(uint64_t TSFlags) { in getDelayType() argument
70 if (TSFlags & SIInstrFlags::TRANS) in getDelayType()
72 if (TSFlags & SIInstrFlags::VALU) in getDelayType()
74 if (TSFlags & SIInstrFlags::SALU) in getDelayType()
371 DelayType Type = getDelayType(MI.getDesc().TSFlags); in runOnMachineBasicBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86IntelInstPrinter.cpp85 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
86 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) in printVecCompareInstr()
88 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
165 if (Desc.TSFlags & X86II::EVEX_K) { in printVecCompareInstr()
175 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
176 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
179 if ((Desc.TSFlags & X86II::OpMapMask) == X86II::TA) { in printVecCompareInstr()
180 assert(!(Desc.TSFlags & X86II::REX_W) && "Unknown W-bit value!"); in printVecCompareInstr()
182 } else if (Desc.TSFlags & X86II::REX_W) { in printVecCompareInstr()
190 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
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H A DX86ATTInstPrinter.cpp118 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
119 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) in printVecCompareInstr()
121 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
199 unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2; in printVecCompareInstr()
201 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
202 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
205 if ((Desc.TSFlags & X86II::OpMapMask) == X86II::TA) { in printVecCompareInstr()
206 assert(!(Desc.TSFlags & X86II::REX_W) && "Unknown W-bit value!"); in printVecCompareInstr()
208 } else if (Desc.TSFlags & X86II::REX_W) { in printVecCompareInstr()
216 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
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H A DX86MCCodeEmitter.cpp373 uint64_t TSFlags, PrefixKind Kind, uint64_t StartByte,
418 static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) { in isDispOrCDisp8() argument
419 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX; in isDispOrCDisp8()
422 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift; in isDispOrCDisp8()
442 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { in getImmFixupKind() argument
443 unsigned Size = X86II::getSizeOfImm(TSFlags); in getImmFixupKind()
444 if (X86II::isImmSigned(TSFlags)) { in getImmFixupKind()
510 !(getImmFixupKind(Desc.TSFlags) == FK_Data_4 && in isPCRel32Branch()
511 X86II::isImmPCRel(Desc.TSFlags))) in isPCRel32Branch()
616 const MCInst &MI, unsigned Op, unsigned RegOpcodeField, uint64_t TSFlags, in emitMemModRMByte() argument
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H A DX86BaseInfo.h882 inline bool isPrefix(uint64_t TSFlags) { in isPrefix() argument
883 return (TSFlags & X86II::FormMask) == PrefixByte; in isPrefix()
887 inline bool isPseudo(uint64_t TSFlags) { in isPseudo() argument
888 return (TSFlags & X86II::FormMask) == Pseudo; in isPseudo()
893 inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) { in getBaseOpcodeFor() argument
894 return TSFlags >> X86II::OpcodeShift; in getBaseOpcodeFor()
897 inline bool hasImm(uint64_t TSFlags) { return (TSFlags & X86II::ImmMask) != 0; } in hasImm() argument
901 inline unsigned getSizeOfImm(uint64_t TSFlags) { in getSizeOfImm() argument
902 switch (TSFlags & X86II::ImmMask) { in getSizeOfImm()
923 inline bool isImmPCRel(uint64_t TSFlags) { in isImmPCRel() argument
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H A DX86InstPrinterCommon.cpp397 uint64_t TSFlags = Desc.TSFlags; in printInstFlags() local
400 if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) in printInstFlags()
403 if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK)) in printInstFlags()
411 if (TSFlags & X86II::EVEX_NF && !X86::isCFCMOVCC(MI->getOpcode())) in printInstFlags()
416 (TSFlags & X86II::ExplicitOpPrefixMask) == X86II::ExplicitVEXPrefix) in printInstFlags()
423 (TSFlags & X86II::ExplicitOpPrefixMask) == X86II::ExplicitEVEXPrefix) in printInstFlags()
432 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags); in printInstFlags()
438 !X86_MC::needsAddressSizeOverride(*MI, STI, MemoryOperand, TSFlags)) { in printInstFlags()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.h41 static inline bool isVRegClass(uint8_t TSFlags) { in isVRegClass() argument
42 return (TSFlags & IsVRegClassShiftMask) >> IsVRegClassShift; in isVRegClass()
46 static inline RISCVVType::VLMUL getLMul(uint8_t TSFlags) { in getLMul() argument
47 return static_cast<RISCVVType::VLMUL>((TSFlags & VLMulShiftMask) >> in getLMul()
52 static inline unsigned getNF(uint8_t TSFlags) { in getNF() argument
53 return static_cast<unsigned>((TSFlags & NFShiftMask) >> NFShift) + 1; in getNF()
148 return RISCVRI::isVRegClass(RC->TSFlags) && in isVRRegClass()
149 RISCVRI::getNF(RC->TSFlags) == 1; in isVRRegClass()
153 return RISCVRI::isVRegClass(RC->TSFlags) && RISCVRI::getNF(RC->TSFlags) > 1; in isVRNRegClass()
157 return RISCVRI::isVRegClass(RC->TSFlags); in isRVVRegClass()
H A DRISCVVectorPeephole.cpp165 !RISCVII::hasVLOp(Src->getDesc().TSFlags) || in tryToReduceVL()
166 !RISCVII::hasSEWOp(Src->getDesc().TSFlags)) in tryToReduceVL()
174 TII->get(RISCV::getRVVMCOpcode(Src->getOpcode())).TSFlags); in tryToReduceVL()
214 if (!RISCVII::hasVLOp(MI.getDesc().TSFlags) || in convertToVLMAX()
215 !RISCVII::hasSEWOp(MI.getDesc().TSFlags)) in convertToVLMAX()
218 auto LMUL = RISCVVType::decodeVLMUL(RISCVII::getLMul(MI.getDesc().TSFlags)); in convertToVLMAX()
335 if (RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags)) in convertToWholeRegister()
491 RISCVII::hasVecPolicyOp(MCID.TSFlags); in convertToUnmasked()
494 assert((RISCVII::hasVecPolicyOp(MaskedMCID.TSFlags) || in convertToUnmasked()
495 !RISCVII::hasVecPolicyOp(MCID.TSFlags)) && in convertToUnmasked()
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H A DRISCVInsertVSETVLI.cpp105 if (!RISCVII::hasSEWOp(MI.getDesc().TSFlags)) in isMaskRegOp()
347 uint64_t TSFlags = MI.getDesc().TSFlags; in getDemanded() local
348 if (RISCVII::hasSEWOp(TSFlags)) { in getDemanded()
350 if (RISCVII::hasVLOp(TSFlags)) in getDemanded()
356 if (!RISCVII::usesMaskPolicy(TSFlags)) in getDemanded()
372 if (RISCVII::hasSEWOp(TSFlags) && MI.getNumExplicitDefs() == 0) { in getDemanded()
409 assert(!RISCVII::hasVLOp(TSFlags)); in getDemanded()
416 if (RISCVII::hasVLOp(MI.getDesc().TSFlags)) { in getDemanded()
473 assert(!RISCVII::hasVLOp(TSFlags)); in getDemanded()
978 const uint64_t TSFlags = MI.getDesc().TSFlags; in computeInfoForInstr() local
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H A DRISCVSelectionDAGInfo.h38 return GenNodeInfo.getDesc(Opcode).TSFlags & RISCVISD::HasPassthruOpMask; in hasPassthruOp()
42 return GenNodeInfo.getDesc(Opcode).TSFlags & RISCVISD::HasMaskOpMask; in hasMaskOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrFormats.td48 let TSFlags{3...0} = VecInstType;
49 let TSFlags{4} = IsLoad;
50 let TSFlags{5} = IsStore;
51 let TSFlags{6} = IsTex;
52 let TSFlags{8...7} = IsSuld;
53 let TSFlags{9} = IsSust;
54 let TSFlags{10} = IsSurfTexQuery;
55 let TSFlags{11} = IsTexModeUnified;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp251 if ((MCID.TSFlags & SIInstrFlags::DS) && in generateWaitCntInfo()
252 (MCID.TSFlags & SIInstrFlags::LGKM_CNT)) { in generateWaitCntInfo()
256 } else if (MCID.TSFlags & SIInstrFlags::FLAT) { in generateWaitCntInfo()
264 else if (MCID.mayLoad() && !(MCID.TSFlags & SIInstrFlags::IsAtomicNoRet)) in generateWaitCntInfo()
272 !(MCID.TSFlags & SIInstrFlags::IsAtomicNoRet)) || in generateWaitCntInfo()
273 ((MCID.TSFlags & SIInstrFlags::MIMG) && !MCID.mayLoad() && in generateWaitCntInfo()
284 (MCID.mayStore() || (MCID.TSFlags & SIInstrFlags::IsAtomicRet))) in generateWaitCntInfo()
286 } else if (MCID.TSFlags & SIInstrFlags::SMRD) { in generateWaitCntInfo()
288 } else if (MCID.TSFlags & SIInstrFlags::EXP) { in generateWaitCntInfo()
305 return MCID.TSFlags & SIInstrFlags::MUBUF || in isVMEM()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFormats.td286 // TSFlags layout should be kept in sync with X86BaseInfo.h.
287 let TSFlags{6-0} = FormBits;
288 let TSFlags{8-7} = OpSizeBits;
289 let TSFlags{10-9} = AdSizeBits;
291 let TSFlags{12-11} = OpPrefixBits{1-0};
292 let TSFlags{16-13} = OpMapBits;
293 let TSFlags{17} = hasREX_W;
294 let TSFlags{21-18} = ImmT.Value;
295 let TSFlags{24-22} = FPForm.Value;
296 let TSFlags{25} = hasLockPrefix;
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H A DX86InstrFMA3Info.cpp155 const X86InstrFMA3Group *llvm::getFMA3Group(unsigned Opcode, uint64_t TSFlags) { in getFMA3Group() argument
158 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group()
162 bool IsFMA3Encoding = ((TSFlags & X86II::EncodingMask) == X86II::VEX && in getFMA3Group()
163 (TSFlags & X86II::OpMapMask) == X86II::T8) || in getFMA3Group()
164 ((TSFlags & X86II::EncodingMask) == X86II::EVEX && in getFMA3Group()
165 ((TSFlags & X86II::OpMapMask) == X86II::T8 || in getFMA3Group()
166 (TSFlags & X86II::OpMapMask) == X86II::T_MAP6)); in getFMA3Group()
167 bool IsFMA3Prefix = (TSFlags & X86II::OpPrefixMask) == X86II::PD || in getFMA3Group()
168 (TSFlags & X86II::OpPrefixMask) == 0; // X86II::PS in getFMA3Group()
175 if (TSFlags & X86II::EVEX_RC) in getFMA3Group()
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H A DX86CompressEVEX.cpp178 uint64_t TSFlags = MI.getDesc().TSFlags; in CompressEVEXImpl() local
181 if ((TSFlags & X86II::EncodingMask) != X86II::EVEX) in CompressEVEXImpl()
185 if (TSFlags & (X86II::EVEX_K | X86II::EVEX_L2)) in CompressEVEXImpl()
222 bool IsND = X86II::hasNewDataDest(TSFlags); in CompressEVEXImpl()
223 if (TSFlags & X86II::EVEX_B && !IsND) in CompressEVEXImpl()
280 switch (NewDesc.TSFlags & X86II::EncodingMask) { in CompressEVEXImpl()
289 assert(IsND && (NewDesc.TSFlags & X86II::EVEX_NF) && in CompressEVEXImpl()
H A DX86EvexToVex.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp243 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
250 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
318 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
336 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
342 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
348 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
381 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
406 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp2()
425 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags; in getType()
515 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in hasNewValue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/
H A DLoongArchBaseInfo.h110 static inline bool isSubjectToAMORdConstraint(uint64_t TSFlags) { in isSubjectToAMORdConstraint() argument
111 return TSFlags & IsSubjectToAMORdConstraintMask; in isSubjectToAMORdConstraint()
115 static inline bool isAMCAS(uint64_t TSFlags) { return TSFlags & IsAMCASMask; } in isAMCAS() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp30 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
51 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { in getHazardType()
61 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) { in getHazardType()
110 uint64_t TSFlags = MI.getDesc().TSFlags; in getBaseOffset() local
111 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); in getBaseOffset()
113 (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift; in getBaseOffset()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp287 uint64_t TSFlags = MCID.TSFlags; in GetInstrType() local
289 isFirst = TSFlags & PPCII::PPC970_First; in GetInstrType()
290 isSingle = TSFlags & PPCII::PPC970_Single; in GetInstrType()
291 isCracked = TSFlags & PPCII::PPC970_Cracked; in GetInstrType()
292 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask); in GetInstrType()

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