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Searched refs:TSFlags (Results 1 – 25 of 127) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.h130 static inline unsigned getFormat(uint64_t TSFlags) { in getFormat() argument
131 return (TSFlags & InstFormatMask) >> InstFormatShift; in getFormat()
134 static inline VLMUL getLMul(uint64_t TSFlags) { in getLMul() argument
135 return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift); in getLMul()
138 static inline bool doesForceTailAgnostic(uint64_t TSFlags) { in doesForceTailAgnostic() argument
139 return TSFlags & ForceTailAgnosticMask; in doesForceTailAgnostic()
142 static inline bool isTiedPseudo(uint64_t TSFlags) { in isTiedPseudo() argument
143 return TSFlags & IsTiedPseudoMask; in isTiedPseudo()
146 static inline bool hasSEWOp(uint64_t TSFlags) { in hasSEWOp() argument
147 return TSFlags & HasSEWOpMask; in hasSEWOp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td73 let TSFlags{6-0} = Type.Value;
77 let TSFlags{7} = isSolo;
80 let TSFlags{8} = isSoloAX;
83 let TSFlags{9} = isRestrictSlot1AOK;
87 let TSFlags{10} = isPredicated;
89 let TSFlags{11} = isPredicatedFalse;
91 let TSFlags{12} = isPredicatedNew;
93 let TSFlags{13} = isPredicateLate; // Late predicate producer insn.
97 let TSFlags{14} = isNewValue; // New-value consumer insn.
99 let TSFlags{15} = hasNewValue; // New-value producer insn.
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h409 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
413 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
417 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
421 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
441 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
445 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
449 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
453 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
457 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
461 return get(Opcode).TSFlags & SIInstrFlags::SOPC; in isSOPC()
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H A DSIInstrFormats.td159 let TSFlags{0} = SALU;
160 let TSFlags{1} = VALU;
162 let TSFlags{2} = SOP1;
163 let TSFlags{3} = SOP2;
164 let TSFlags{4} = SOPC;
165 let TSFlags{5} = SOPK;
166 let TSFlags{6} = SOPP;
168 let TSFlags{7} = VOP1;
169 let TSFlags{8} = VOP2;
170 let TSFlags{9} = VOPC;
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H A DR600InstrFormats.td53 let TSFlags{4} = Trig;
54 let TSFlags{5} = Op3;
58 let TSFlags{6} = isVector;
59 let TSFlags{8-7} = FlagOperandIdx;
60 let TSFlags{9} = HasNativeOperands;
61 let TSFlags{10} = Op1;
62 let TSFlags{11} = Op2;
63 let TSFlags{12} = VTXInst;
64 let TSFlags{13} = TEXInst;
65 let TSFlags{14} = ALUInst;
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H A DAMDGPUInsertDelayAlu.cpp48 if (MI.getDesc().TSFlags & VA_VDST_0) in instructionWaitsForVALU()
63 static DelayType getDelayType(uint64_t TSFlags) { in getDelayType() argument
64 if (TSFlags & SIInstrFlags::TRANS) in getDelayType()
66 if (TSFlags & SIInstrFlags::VALU) in getDelayType()
68 if (TSFlags & SIInstrFlags::SALU) in getDelayType()
355 DelayType Type = getDelayType(MI.getDesc().TSFlags); in runOnMachineBasicBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ATTInstPrinter.cpp102 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
103 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) in printVecCompareInstr()
105 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
174 unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2; in printVecCompareInstr()
176 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
177 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
180 if ((Desc.TSFlags & X86II::OpMapMask) == X86II::TA) { in printVecCompareInstr()
181 assert(!(Desc.TSFlags & X86II::REX_W) && "Unknown W-bit value!"); in printVecCompareInstr()
183 } else if (Desc.TSFlags & X86II::REX_W) { in printVecCompareInstr()
191 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
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H A DX86IntelInstPrinter.cpp85 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
86 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) in printVecCompareInstr()
88 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) in printVecCompareInstr()
156 if (Desc.TSFlags & X86II::EVEX_K) { in printVecCompareInstr()
166 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { in printVecCompareInstr()
167 if (Desc.TSFlags & X86II::EVEX_B) { in printVecCompareInstr()
170 if ((Desc.TSFlags & X86II::OpMapMask) == X86II::TA) { in printVecCompareInstr()
171 assert(!(Desc.TSFlags & X86II::REX_W) && "Unknown W-bit value!"); in printVecCompareInstr()
173 } else if (Desc.TSFlags & X86II::REX_W) { in printVecCompareInstr()
181 if (Desc.TSFlags & X86II::EVEX_L2) in printVecCompareInstr()
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H A DX86MCCodeEmitter.cpp370 uint64_t TSFlags, PrefixKind Kind, uint64_t StartByte,
415 static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) { in isDispOrCDisp8() argument
416 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX; in isDispOrCDisp8()
419 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift; in isDispOrCDisp8()
439 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { in getImmFixupKind() argument
440 unsigned Size = X86II::getSizeOfImm(TSFlags); in getImmFixupKind()
441 bool isPCRel = X86II::isImmPCRel(TSFlags); in getImmFixupKind()
443 if (X86II::isImmSigned(TSFlags)) { in getImmFixupKind()
495 getImmFixupKind(Desc.TSFlags) != FK_PCRel_4) in isPCRel32Branch()
608 const MCInst &MI, unsigned Op, unsigned RegOpcodeField, uint64_t TSFlags, in emitMemModRMByte() argument
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H A DX86BaseInfo.h879 inline bool isPrefix(uint64_t TSFlags) { in isPrefix() argument
880 return (TSFlags & X86II::FormMask) == PrefixByte; in isPrefix()
884 inline bool isPseudo(uint64_t TSFlags) { in isPseudo() argument
885 return (TSFlags & X86II::FormMask) == Pseudo; in isPseudo()
890 inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) { in getBaseOpcodeFor() argument
891 return TSFlags >> X86II::OpcodeShift; in getBaseOpcodeFor()
894 inline bool hasImm(uint64_t TSFlags) { return (TSFlags & X86II::ImmMask) != 0; } in hasImm() argument
898 inline unsigned getSizeOfImm(uint64_t TSFlags) { in getSizeOfImm() argument
899 switch (TSFlags & X86II::ImmMask) { in getSizeOfImm()
920 inline bool isImmPCRel(uint64_t TSFlags) { in isImmPCRel() argument
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H A DX86InstPrinterCommon.cpp383 uint64_t TSFlags = Desc.TSFlags; in printInstFlags() local
386 if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) in printInstFlags()
389 if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK)) in printInstFlags()
397 if (TSFlags & X86II::EVEX_NF && !X86::isCFCMOVCC(MI->getOpcode())) in printInstFlags()
402 (TSFlags & X86II::ExplicitOpPrefixMask) == X86II::ExplicitVEXPrefix) in printInstFlags()
409 (TSFlags & X86II::ExplicitOpPrefixMask) == X86II::ExplicitEVEXPrefix) in printInstFlags()
418 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags); in printInstFlags()
424 !X86_MC::needsAddressSizeOverride(*MI, STI, MemoryOperand, TSFlags)) { in printInstFlags()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrFormats.td49 let TSFlags{3...0} = VecInstType;
50 let TSFlags{4...4} = IsSimpleMove;
51 let TSFlags{5...5} = IsLoad;
52 let TSFlags{6...6} = IsStore;
53 let TSFlags{7} = IsTex;
54 let TSFlags{9...8} = IsSuld;
55 let TSFlags{10} = IsSust;
56 let TSFlags{11} = IsSurfTexQuery;
57 let TSFlags{12} = IsTexModeUnified;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.h41 static inline bool isVRegClass(uint64_t TSFlags) { in isVRegClass() argument
42 return TSFlags & IsVRegClassShiftMask >> IsVRegClassShift; in isVRegClass()
46 static inline RISCVII::VLMUL getLMul(uint64_t TSFlags) { in getLMul() argument
47 return static_cast<RISCVII::VLMUL>((TSFlags & VLMulShiftMask) >> VLMulShift); in getLMul()
51 static inline unsigned getNF(uint64_t TSFlags) { in getNF() argument
52 return static_cast<unsigned>((TSFlags & NFShiftMask) >> NFShift) + 1; in getNF()
152 return RISCVRI::isVRegClass(RC->TSFlags) && in isVRRegClass()
153 RISCVRI::getNF(RC->TSFlags) == 1; in isVRRegClass()
157 return RISCVRI::isVRegClass(RC->TSFlags) && RISCVRI::getNF(RC->TSFlags) > 1; in isVRNRegClass()
161 return RISCVRI::isVRegClass(RC->TSFlags); in isRVVRegClass()
H A DRISCVVectorPeephole.cpp81 if (!RISCVII::hasVLOp(MI.getDesc().TSFlags) || in convertToVLMAX()
82 !RISCVII::hasSEWOp(MI.getDesc().TSFlags)) in convertToVLMAX()
107 auto LMUL = RISCVVType::decodeVLMUL(RISCVII::getLMul(MI.getDesc().TSFlags)); in convertToVLMAX()
217 RISCVII::hasVecPolicyOp(MCID.TSFlags); in convertToUnmasked()
221 assert(RISCVII::hasVecPolicyOp(MaskedMCID.TSFlags) == in convertToUnmasked()
222 RISCVII::hasVecPolicyOp(MCID.TSFlags) && in convertToUnmasked()
H A DRISCVInsertVSETVLI.cpp174 if (!RISCVII::hasSEWOp(MI.getDesc().TSFlags)) in isMaskRegOp()
402 uint64_t TSFlags = MI.getDesc().TSFlags; in getDemanded() local
403 if (RISCVII::hasSEWOp(TSFlags)) { in getDemanded()
405 if (RISCVII::hasVLOp(TSFlags)) in getDemanded()
411 if (!RISCVII::usesMaskPolicy(TSFlags)) in getDemanded()
427 if (RISCVII::hasSEWOp(TSFlags) && MI.getNumExplicitDefs() == 0) { in getDemanded()
463 assert(!RISCVII::hasVLOp(TSFlags)); in getDemanded()
470 if (RISCVII::hasVLOp(MI.getDesc().TSFlags)) { in getDemanded()
999 const uint64_t TSFlags = MI.getDesc().TSFlags; in computeInfoForInstr() local
1009 if (RISCVII::hasVecPolicyOp(TSFlags)) { in computeInfoForInstr()
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H A DRISCVInstrFormats.td170 let TSFlags{4-0} = format.Value;
174 let TSFlags{7-5} = RVVConstraint.Value;
177 let TSFlags{10-8} = VLMul;
180 let TSFlags{11} = ForceTailAgnostic;
183 let TSFlags{12} = IsTiedPseudo;
186 let TSFlags{13} = HasSEWOp;
189 let TSFlags{14} = HasVLOp;
192 let TSFlags{15} = HasVecPolicyOp;
195 let TSFlags{16} = IsRVVWideningReduction;
198 let TSFlags{17} = UsesMaskPolicy;
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp250 if ((MCID.TSFlags & SIInstrFlags::DS) && in generateWaitCntInfo()
251 (MCID.TSFlags & SIInstrFlags::LGKM_CNT)) { in generateWaitCntInfo()
255 } else if (MCID.TSFlags & SIInstrFlags::FLAT) { in generateWaitCntInfo()
263 else if (MCID.mayLoad() && !(MCID.TSFlags & SIInstrFlags::IsAtomicNoRet)) in generateWaitCntInfo()
271 !(MCID.TSFlags & SIInstrFlags::IsAtomicNoRet)) || in generateWaitCntInfo()
272 ((MCID.TSFlags & SIInstrFlags::MIMG) && !MCID.mayLoad() && in generateWaitCntInfo()
283 (MCID.mayStore() || (MCID.TSFlags & SIInstrFlags::IsAtomicRet))) in generateWaitCntInfo()
285 } else if (MCID.TSFlags & SIInstrFlags::SMRD) { in generateWaitCntInfo()
287 } else if (MCID.TSFlags & SIInstrFlags::EXP) { in generateWaitCntInfo()
304 return MCID.TSFlags & SIInstrFlags::MUBUF || in isVMEM()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFormats.td285 // TSFlags layout should be kept in sync with X86BaseInfo.h.
286 let TSFlags{6-0} = FormBits;
287 let TSFlags{8-7} = OpSizeBits;
288 let TSFlags{10-9} = AdSizeBits;
290 let TSFlags{12-11} = OpPrefixBits{1-0};
291 let TSFlags{16-13} = OpMapBits;
292 let TSFlags{17} = hasREX_W;
293 let TSFlags{21-18} = ImmT.Value;
294 let TSFlags{24-22} = FPForm.Value;
295 let TSFlags{25} = hasLockPrefix;
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H A DX86InstrFMA3Info.cpp141 const X86InstrFMA3Group *llvm::getFMA3Group(unsigned Opcode, uint64_t TSFlags) { in getFMA3Group() argument
144 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group()
148 bool IsFMA3Encoding = ((TSFlags & X86II::EncodingMask) == X86II::VEX && in getFMA3Group()
149 (TSFlags & X86II::OpMapMask) == X86II::T8) || in getFMA3Group()
150 ((TSFlags & X86II::EncodingMask) == X86II::EVEX && in getFMA3Group()
151 ((TSFlags & X86II::OpMapMask) == X86II::T8 || in getFMA3Group()
152 (TSFlags & X86II::OpMapMask) == X86II::T_MAP6)); in getFMA3Group()
153 bool IsFMA3Prefix = (TSFlags & X86II::OpPrefixMask) == X86II::PD; in getFMA3Group()
160 if (TSFlags & X86II::EVEX_RC) in getFMA3Group()
162 else if (TSFlags & X86II::EVEX_B) in getFMA3Group()
H A DX86CompressEVEX.cpp178 uint64_t TSFlags = MI.getDesc().TSFlags; in CompressEVEXImpl() local
181 if ((TSFlags & X86II::EncodingMask) != X86II::EVEX) in CompressEVEXImpl()
185 if (TSFlags & (X86II::EVEX_K | X86II::EVEX_L2)) in CompressEVEXImpl()
222 bool IsND = X86II::hasNewDataDest(TSFlags); in CompressEVEXImpl()
223 if (TSFlags & X86II::EVEX_B && !IsND) in CompressEVEXImpl()
256 switch (NewDesc.TSFlags & X86II::EncodingMask) { in CompressEVEXImpl()
265 assert(IsND && (NewDesc.TSFlags & X86II::EVEX_NF) && in CompressEVEXImpl()
H A DX86EvexToVex.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp243 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
250 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
318 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
336 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
342 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
348 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
381 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
406 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp2()
425 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags; in getType()
515 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in hasNewValue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp32 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
53 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { in getHazardType()
63 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) { in getHazardType()
112 uint64_t TSFlags = MI.getDesc().TSFlags; in getBaseOffset() local
113 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); in getBaseOffset()
115 (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift; in getBaseOffset()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp287 uint64_t TSFlags = MCID.TSFlags; in GetInstrType() local
289 isFirst = TSFlags & PPCII::PPC970_First; in GetInstrType()
290 isSingle = TSFlags & PPCII::PPC970_Single; in GetInstrType()
291 isCracked = TSFlags & PPCII::PPC970_Cracked; in GetInstrType()
292 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask); in GetInstrType()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp403 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; in decodeAVLdSt() local
404 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 in decodeAVLdSt()
414 if (TSFlags & SIInstrFlags::DS) { in decodeAVLdSt()
615 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DPP) { in getInstruction()
619 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) in getInstruction()
621 else if ((MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) || in getInstruction()
627 else if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3) in getInstruction()
644 if ((MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DS) && in getInstruction()
649 if (MCII->get(MI.getOpcode()).TSFlags & in getInstruction()
655 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? in getInstruction()
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