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Searched refs:TRCEVENTCTL0R (Results 1 – 3 of 3) sorted by relevance

/freebsd/sys/arm64/coresight/
H A Dcoresight_etm4x.h67 #define TRCEVENTCTL0R 0x020 /* Trace Event Control 0 Register */ macro
H A Dcoresight_etm4x.c90 bus_write_4(sc->res, TRCEVENTCTL0R, 0); in etm_prepare()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SystemOperands.td1127 def : RWSysReg<"TRCEVENTCTL0R", 0b10, 0b001, 0b0000, 0b1000, 0b000>;