xref: /freebsd/sys/arm/mv/mvreg.h (revision 95ee2897e98f5d444f26ed2334cc7c439f9c16c6)
1 /*-
2  * SPDX-License-Identifier: BSD-3-Clause
3  *
4  * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD.
5  * All rights reserved.
6  *
7  * Developed by Semihalf.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. Neither the name of MARVELL nor the names of contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31  * SUCH DAMAGE.
32  */
33 
34 #ifndef _MVREG_H_
35 #define _MVREG_H_
36 
37 #include <arm/mv/mvwin.h>
38 
39 #if defined(SOC_MV_DISCOVERY)
40 #define IRQ_CAUSE_ERROR		0x0
41 #define IRQ_CAUSE		0x4
42 #define IRQ_CAUSE_HI		0x8
43 #define IRQ_MASK_ERROR		0xC
44 #define IRQ_MASK		0x10
45 #define IRQ_MASK_HI		0x14
46 #define IRQ_CAUSE_SELECT	0x18
47 #define FIQ_MASK_ERROR		0x1C
48 #define FIQ_MASK		0x20
49 #define FIQ_MASK_HI		0x24
50 #define FIQ_CAUSE_SELECT	0x28
51 #define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C
52 #define ENDPOINT_IRQ_MASK(n)	0x30
53 #define ENDPOINT_IRQ_MASK_HI(n)	0x34
54 #define ENDPOINT_IRQ_CAUSE_SELECT 0x38
55 #else
56 #define IRQ_CAUSE		0x0
57 #define IRQ_MASK		0x4
58 #define FIQ_MASK		0x8
59 #define ENDPOINT_IRQ_MASK(n)	0xC
60 #define IRQ_CAUSE_HI		0x10
61 #define IRQ_MASK_HI		0x14
62 #define FIQ_MASK_HI		0x18
63 #define ENDPOINT_IRQ_MASK_HI(n)	0x1C
64 #define ENDPOINT_IRQ_MASK_ERROR(n) (-1)
65 #define IRQ_CAUSE_ERROR		(-1)		/* Fake defines for unified */
66 #define IRQ_MASK_ERROR		(-1)		/* interrupt controller code */
67 #endif
68 
69 #define MAIN_IRQ_NUM		116
70 #define ERR_IRQ_NUM		32
71 #define ERR_IRQ			(MAIN_IRQ_NUM)
72 #define MSI_IRQ			(ERR_IRQ + ERR_IRQ_NUM)
73 
74 #define MSI_IRQ_NUM		32
75 
76 #define IRQ_CPU_SELF		0x00000001
77 #define	BRIDGE_IRQ_CAUSE_ARMADAXP	0x68
78 #define	IRQ_TIMER0_ARMADAXP		0x00000001
79 #define	IRQ_TIMER1_ARMADAXP		0x00000002
80 #define	IRQ_TIMER_WD_ARMADAXP		0x00000004
81 
82 #define BRIDGE_IRQ_CAUSE	0x10
83 #define IRQ_CPU_SELF		0x00000001
84 #define IRQ_TIMER0		0x00000002
85 #define IRQ_TIMER1		0x00000004
86 #define IRQ_TIMER_WD		0x00000008
87 
88 #define BRIDGE_IRQ_MASK		0x14
89 #define IRQ_CPU_MASK		0x00000001
90 #define IRQ_TIMER0_MASK		0x00000002
91 #define IRQ_TIMER1_MASK		0x00000004
92 #define IRQ_TIMER_WD_MASK	0x00000008
93 
94 #define IRQ_CPU_SELF_CLR	(~IRQ_CPU_SELF)
95 #define IRQ_TIMER0_CLR		(~IRQ_TIMER0)
96 #define IRQ_TIMER_WD_CLR	(~IRQ_TIMER_WD)
97 
98 #define	IRQ_TIMER0_CLR_ARMADAXP		(~IRQ_TIMER0_ARMADAXP)
99 #define	IRQ_TIMER_WD_CLR_ARMADAXP	(~IRQ_TIMER_WD_ARMADAXP)
100 
101 /*
102  * System reset
103  */
104 #define	RSTOUTn_MASK_ARMV7	0x60
105 #define	SYSTEM_SOFT_RESET_ARMV7	0x64
106 #define	SOFT_RST_OUT_EN_ARMV7	0x00000001
107 #define	SYS_SOFT_RST_ARMV7	0x00000001
108 
109 #define RSTOUTn_MASK		0x8
110 #define SOFT_RST_OUT_EN		0x00000004
111 #define SYSTEM_SOFT_RESET	0xc
112 #define SYS_SOFT_RST		0x00000001
113 #define RSTOUTn_MASK_WD		0x400
114 #define WD_RSTOUTn_MASK		0x4
115 #define WD_GLOBAL_MASK		0x00000100
116 #define WD_CPU0_MASK		0x00000001
117 #define WD_RST_OUT_EN		0x00000002
118 
119 /*
120  * Power Control
121  */
122 #if defined(SOC_MV_KIRKWOOD)
123 #define CPU_PM_CTRL		0x18
124 #else
125 #define CPU_PM_CTRL		0x1C
126 #endif
127 #define CPU_PM_CTRL_NONE	0
128 #define CPU_PM_CTRL_ALL		~0x0
129 
130 #if defined(SOC_MV_KIRKWOOD)
131 #define CPU_PM_CTRL_GE0		(1 << 0)
132 #define CPU_PM_CTRL_PEX0_PHY	(1 << 1)
133 #define CPU_PM_CTRL_PEX0	(1 << 2)
134 #define CPU_PM_CTRL_USB0	(1 << 3)
135 #define CPU_PM_CTRL_SDIO	(1 << 4)
136 #define CPU_PM_CTRL_TSU		(1 << 5)
137 #define CPU_PM_CTRL_DUNIT	(1 << 6)
138 #define CPU_PM_CTRL_RUNIT	(1 << 7)
139 #define CPU_PM_CTRL_XOR0	(1 << 8)
140 #define CPU_PM_CTRL_AUDIO	(1 << 9)
141 #define CPU_PM_CTRL_SATA0	(1 << 14)
142 #define CPU_PM_CTRL_SATA1	(1 << 15)
143 #define CPU_PM_CTRL_XOR1	(1 << 16)
144 #define CPU_PM_CTRL_CRYPTO	(1 << 17)
145 #define CPU_PM_CTRL_GE1		(1 << 19)
146 #define CPU_PM_CTRL_TDM		(1 << 20)
147 #define CPU_PM_CTRL_XOR		(CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1)
148 #define CPU_PM_CTRL_USB(u)	(CPU_PM_CTRL_USB0)
149 #define CPU_PM_CTRL_SATA	(CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1)
150 #define CPU_PM_CTRL_GE(u)	(CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \
151 				(1 - (u)))
152 #define CPU_PM_CTRL_IDMA	(CPU_PM_CTRL_NONE)
153 #elif defined(SOC_MV_DISCOVERY)
154 #define CPU_PM_CTRL_GE0		(1 << 1)
155 #define CPU_PM_CTRL_GE1		(1 << 2)
156 #define CPU_PM_CTRL_PEX00	(1 << 5)
157 #define CPU_PM_CTRL_PEX01	(1 << 6)
158 #define CPU_PM_CTRL_PEX02	(1 << 7)
159 #define CPU_PM_CTRL_PEX03	(1 << 8)
160 #define CPU_PM_CTRL_PEX10	(1 << 9)
161 #define CPU_PM_CTRL_PEX11	(1 << 10)
162 #define CPU_PM_CTRL_PEX12	(1 << 11)
163 #define CPU_PM_CTRL_PEX13	(1 << 12)
164 #define CPU_PM_CTRL_SATA0_PHY	(1 << 13)
165 #define CPU_PM_CTRL_SATA0	(1 << 14)
166 #define CPU_PM_CTRL_SATA1_PHY	(1 << 15)
167 #define CPU_PM_CTRL_SATA1	(1 << 16)
168 #define CPU_PM_CTRL_USB0	(1 << 17)
169 #define CPU_PM_CTRL_USB1	(1 << 18)
170 #define CPU_PM_CTRL_USB2	(1 << 19)
171 #define CPU_PM_CTRL_IDMA	(1 << 20)
172 #define CPU_PM_CTRL_XOR		(1 << 21)
173 #define CPU_PM_CTRL_CRYPTO	(1 << 22)
174 #define CPU_PM_CTRL_DEVICE	(1 << 23)
175 #define CPU_PM_CTRL_USB(u)	(1 << (17 + (u)))
176 #define CPU_PM_CTRL_SATA	(CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1)
177 #define CPU_PM_CTRL_GE(u)	(CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \
178 				(1 - (u)))
179 #else
180 #define CPU_PM_CTRL_CRYPTO	(CPU_PM_CTRL_NONE)
181 #define CPU_PM_CTRL_IDMA	(CPU_PM_CTRL_NONE)
182 #define CPU_PM_CTRL_XOR		(CPU_PM_CTRL_NONE)
183 #define CPU_PM_CTRL_SATA	(CPU_PM_CTRL_NONE)
184 #define CPU_PM_CTRL_USB(u)	(CPU_PM_CTRL_NONE)
185 #define CPU_PM_CTRL_GE(u)	(CPU_PM_CTRL_NONE)
186 #endif
187 
188 /*
189  * Timers
190  */
191 #define CPU_TIMERS_BASE		0x300
192 #define CPU_TIMER_CONTROL	0x0
193 #define CPU_TIMER0_EN		0x00000001
194 #define CPU_TIMER0_AUTO		0x00000002
195 #define CPU_TIMER1_EN		0x00000004
196 #define CPU_TIMER1_AUTO		0x00000008
197 #define	CPU_TIMER2_EN		0x00000010
198 #define	CPU_TIMER2_AUTO		0x00000020
199 #define	CPU_TIMER_WD_EN		0x00000100
200 #define	CPU_TIMER_WD_AUTO	0x00000200
201 /* 25MHz mode is Armada XP - specific */
202 #define CPU_TIMER_WD_25MHZ_EN	0x00000400
203 #define CPU_TIMER0_25MHZ_EN	0x00000800
204 #define CPU_TIMER1_25MHZ_EN	0x00001000
205 #define CPU_TIMER0_REL		0x10
206 #define CPU_TIMER0		0x14
207 
208 /*
209  * SATA
210  */
211 #define SATA_CHAN_NUM			2
212 
213 #define EDMA_REGISTERS_OFFSET		0x2000
214 #define EDMA_REGISTERS_SIZE		0x2000
215 #define SATA_EDMA_BASE(ch)		(EDMA_REGISTERS_OFFSET + \
216     ((ch) * EDMA_REGISTERS_SIZE))
217 
218 /* SATAHC registers */
219 #define SATA_CR				0x000 /* Configuration Reg. */
220 #define SATA_CR_NODMABS			(1 << 8)
221 #define SATA_CR_NOEDMABS		(1 << 9)
222 #define SATA_CR_NOPRDPBS		(1 << 10)
223 #define SATA_CR_COALDIS(ch)		(1 << (24 + ch))
224 
225 /* Interrupt Coalescing Threshold Reg. */
226 #define SATA_ICTR			0x00C
227 #define SATA_ICTR_MAX			((1 << 8) - 1)
228 
229 /* Interrupt Time Threshold Reg. */
230 #define SATA_ITTR			0x010
231 #define SATA_ITTR_MAX			((1 << 24) - 1)
232 
233 #define SATA_ICR			0x014 /* Interrupt Cause Reg. */
234 #define SATA_ICR_DMADONE(ch)		(1 << (ch))
235 #define SATA_ICR_COAL			(1 << 4)
236 #define SATA_ICR_DEV(ch)		(1 << (8 + ch))
237 
238 #define SATA_MICR			0x020 /* Main Interrupt Cause Reg. */
239 #define SATA_MICR_ERR(ch)		(1 << (2 * ch))
240 #define SATA_MICR_DONE(ch)		(1 << ((2 * ch) + 1))
241 #define SATA_MICR_DMADONE(ch)		(1 << (4 + ch))
242 #define SATA_MICR_COAL			(1 << 8)
243 
244 #define SATA_MIMR			0x024 /*  Main Interrupt Mask Reg. */
245 
246 /* Shadow registers */
247 #define SATA_SHADOWR_BASE(ch)		(SATA_EDMA_BASE(ch) + 0x100)
248 #define SATA_SHADOWR_CONTROL(ch)	(SATA_EDMA_BASE(ch) + 0x120)
249 
250 /* SATA registers */
251 #define SATA_SATA_SSTATUS(ch)		(SATA_EDMA_BASE(ch) + 0x300)
252 #define SATA_SATA_SERROR(ch)		(SATA_EDMA_BASE(ch) + 0x304)
253 #define SATA_SATA_SCONTROL(ch)		(SATA_EDMA_BASE(ch) + 0x308)
254 #define SATA_SATA_FISICR(ch)		(SATA_EDMA_BASE(ch) + 0x364)
255 
256 /* EDMA registers */
257 #define SATA_EDMA_CFG(ch)		(SATA_EDMA_BASE(ch) + 0x000)
258 #define SATA_EDMA_CFG_QL128		(1 << 19)
259 #define SATA_EDMA_CFG_HQCACHE		(1 << 22)
260 
261 #define SATA_EDMA_IECR(ch)		(SATA_EDMA_BASE(ch) + 0x008)
262 
263 #define SATA_EDMA_IEMR(ch)		(SATA_EDMA_BASE(ch) + 0x00C)
264 #define SATA_EDMA_REQBAHR(ch)		(SATA_EDMA_BASE(ch) + 0x010)
265 #define SATA_EDMA_REQIPR(ch)		(SATA_EDMA_BASE(ch) + 0x014)
266 #define SATA_EDMA_REQOPR(ch)		(SATA_EDMA_BASE(ch) + 0x018)
267 #define SATA_EDMA_RESBAHR(ch)		(SATA_EDMA_BASE(ch) + 0x01C)
268 #define SATA_EDMA_RESIPR(ch)		(SATA_EDMA_BASE(ch) + 0x020)
269 #define SATA_EDMA_RESOPR(ch)		(SATA_EDMA_BASE(ch) + 0x024)
270 
271 #define SATA_EDMA_CMD(ch)		(SATA_EDMA_BASE(ch) + 0x028)
272 #define SATA_EDMA_CMD_ENABLE		(1 << 0)
273 #define SATA_EDMA_CMD_DISABLE		(1 << 1)
274 #define SATA_EDMA_CMD_RESET		(1 << 2)
275 
276 #define SATA_EDMA_STATUS(ch)		(SATA_EDMA_BASE(ch) + 0x030)
277 #define SATA_EDMA_STATUS_IDLE		(1 << 7)
278 
279 /* Offset to extract input slot from REQIPR register */
280 #define SATA_EDMA_REQIS_OFS		5
281 
282 /* Offset to extract input slot from RESOPR register */
283 #define SATA_EDMA_RESOS_OFS		3
284 
285 /*
286  * GPIO
287  */
288 #define GPIO_DATA_OUT		0x00
289 #define GPIO_DATA_OUT_EN_CTRL	0x04
290 #define GPIO_BLINK_EN		0x08
291 #define GPIO_DATA_IN_POLAR	0x0c
292 #define GPIO_DATA_IN		0x10
293 #define GPIO_INT_CAUSE		0x14
294 #define GPIO_INT_EDGE_MASK	0x18
295 #define GPIO_INT_LEV_MASK	0x1c
296 
297 #define GPIO(n)			(1 << (n))
298 #define MV_GPIO_MAX_NPINS	64
299 
300 #define MV_GPIO_IN_NONE			0x0
301 #define MV_GPIO_IN_POL_LOW		(1 << 16)
302 #define MV_GPIO_IN_IRQ_EDGE		(2 << 16)
303 #define MV_GPIO_IN_IRQ_LEVEL		(4 << 16)
304 #define MV_GPIO_IN_IRQ_DOUBLE_EDGE	(8 << 16)
305 #define MV_GPIO_IN_DEBOUNCE		(16 << 16)
306 #define MV_GPIO_OUT_NONE		0x0
307 #define MV_GPIO_OUT_BLINK		0x1
308 #define MV_GPIO_OUT_OPEN_DRAIN		0x2
309 #define MV_GPIO_OUT_OPEN_SRC		0x4
310 
311 #if defined(SOC_MV_ORION)
312 #define SAMPLE_AT_RESET		0x10
313 #elif defined(SOC_MV_KIRKWOOD)
314 #define SAMPLE_AT_RESET		0x30
315 #endif
316 #define	SAMPLE_AT_RESET_ARMADA38X	0x400
317 #define	SAMPLE_AT_RESET_LO		0x30
318 #define	SAMPLE_AT_RESET_HI		0x34
319 
320 /*
321  * Clocks
322  */
323 #if defined(SOC_MV_ORION)
324 #define TCLK_MASK		0x00000300
325 #define TCLK_SHIFT		0x08
326 #elif defined(SOC_MV_DISCOVERY)
327 #define TCLK_MASK		0x00000180
328 #define TCLK_SHIFT		0x07
329 #endif
330 
331 #define	TCLK_MASK_ARMADA38X		0x00008000
332 #define	TCLK_SHIFT_ARMADA38X		15
333 
334 #define TCLK_100MHZ		100000000
335 #define TCLK_125MHZ		125000000
336 #define TCLK_133MHZ		133333333
337 #define TCLK_150MHZ		150000000
338 #define TCLK_166MHZ		166666667
339 #define TCLK_200MHZ		200000000
340 #define TCLK_250MHZ		250000000
341 #define TCLK_300MHZ		300000000
342 #define TCLK_667MHZ		667000000
343 
344 #define	A38X_CPU_DDR_CLK_MASK	0x00007c00
345 #define	A38X_CPU_DDR_CLK_SHIFT	10
346 
347 /*
348  * CPU Cache Configuration
349  */
350 
351 #define CPU_CONFIG		0x00000000
352 #define CPU_CONFIG_IC_PREF	0x00010000
353 #define CPU_CONFIG_DC_PREF	0x00020000
354 #define CPU_CONTROL		0x00000004
355 #define CPU_CONTROL_L2_SIZE	0x00200000	/* Only on Discovery */
356 #define CPU_CONTROL_L2_MODE	0x00020000	/* Only on Discovery */
357 #define CPU_L2_CONFIG		0x00000028	/* Only on Kirkwood */
358 #define CPU_L2_CONFIG_MODE	0x00000010	/* Only on Kirkwood */
359 
360 /*
361  * PCI Express port control (CPU Control registers)
362  */
363 #define CPU_CONTROL_PCIE_DISABLE(n)	(1 << (3 * (n)))
364 
365 /*
366  * Vendor ID
367  */
368 #define PCI_VENDORID_MRVL	0x11AB
369 #define PCI_VENDORID_MRVL2	0x1B4B
370 
371 /*
372  * Chip ID
373  */
374 #define MV_DEV_88F5181		0x5181
375 #define MV_DEV_88F5182		0x5182
376 #define MV_DEV_88F5281		0x5281
377 #define MV_DEV_88F6281		0x6281
378 #define MV_DEV_88F6282		0x6282
379 #define MV_DEV_88F6781		0x6781
380 #define MV_DEV_88F6828		0x6828
381 #define MV_DEV_88F6820		0x6820
382 #define MV_DEV_88F6810		0x6810
383 #define MV_DEV_MV78100_Z0	0x6381
384 #define MV_DEV_MV78100		0x7810
385 #define MV_DEV_MV78130		0x7813
386 #define MV_DEV_MV78160		0x7816
387 #define MV_DEV_MV78230		0x7823
388 #define MV_DEV_MV78260		0x7826
389 #define MV_DEV_MV78460		0x7846
390 #define MV_DEV_88RC8180		0x8180
391 #define MV_DEV_88RC9480		0x9480
392 #define MV_DEV_88RC9580		0x9580
393 
394 #define MV_DEV_FAMILY_MASK	0xff00
395 #define MV_DEV_DISCOVERY	0x7800
396 #define	MV_DEV_ARMADA38X	0x6800
397 
398 /*
399  * Doorbell register control
400  */
401 #define MV_DRBL_PCIE_TO_CPU	0
402 #define MV_DRBL_CPU_TO_PCIE	1
403 
404 #define MV_DRBL_CAUSE(d,u)	(0x10 * (u) + 0x8 * (d))
405 #define MV_DRBL_MASK(d,u)	(0x10 * (u) + 0x8 * (d) + 0x4)
406 #define MV_DRBL_MSG(m,d,u)	(0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30)
407 
408 /*
409  * SCU
410  */
411 #define	MV_SCU_BASE		(MV_BASE + 0xc000)
412 #define	MV_SCU_REGS_LEN		0x100
413 #define	MV_SCU_REG_CTRL		0x00
414 #define	MV_SCU_REG_CONFIG	0x04
415 #define	MV_SCU_ENABLE		(1 << 0)
416 #define	MV_SCU_SL_L2_ENABLE	(1 << 3)
417 #define	SCU_CFG_REG_NCPU_MASK	0x3
418 
419 /*
420  * PMSU
421  */
422 #define	MV_PMSU_BASE		(MV_BASE + 0x22000)
423 #define	MV_PMSU_REGS_LEN	0x1000
424 #define	PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu)	(((cpu) * 0x100) + 0x124)
425 
426 /*
427  * CPU RESET
428  */
429 #define	MV_CPU_RESET_BASE	(MV_BASE + 0x20800)
430 #define	MV_CPU_RESET_REGS_LEN	0x8
431 #define	CPU_RESET_OFFSET(cpu)	((cpu) * 0x8)
432 #define	CPU_RESET_ASSERT	0x1
433 
434 #define	MV_MBUS_CTRL_BASE	(MV_BASE + 0x20420)
435 #define	MV_MBUS_CTRL_REGS_LEN	0x10
436 
437 #endif /* _MVREG_H_ */
438