| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| H A D | SystemZMCTargetDesc.cpp | 47 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, 48 SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, 49 SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, 50 SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L}; 53 SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, 54 SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H, 55 SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H, 56 SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H}; 59 SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, 60 SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, [all …]
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| H A D | SystemZELFObjectWriter.cpp | 53 case SystemZ::FK_390_U8Imm: in getAbsoluteReloc() 54 case SystemZ::FK_390_S8Imm: in getAbsoluteReloc() 56 case SystemZ::FK_390_U12Imm: in getAbsoluteReloc() 59 case SystemZ::FK_390_U16Imm: in getAbsoluteReloc() 60 case SystemZ::FK_390_S16Imm: in getAbsoluteReloc() 62 case SystemZ::FK_390_S20Imm: in getAbsoluteReloc() 65 case SystemZ::FK_390_U32Imm: in getAbsoluteReloc() 66 case SystemZ::FK_390_S32Imm: in getAbsoluteReloc() 79 case SystemZ::FK_390_U16Imm: in getPCRelReloc() 80 case SystemZ::FK_390_S16Imm: in getPCRelReloc() [all …]
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| H A D | SystemZMCObjectWriter.cpp | |
| H A D | SystemZMCAsmBackend.cpp | 58 case SystemZ::FK_390_PC12DBL: in extractBitsForFixup() 60 case SystemZ::FK_390_PC16DBL: in extractBitsForFixup() 62 case SystemZ::FK_390_PC24DBL: in extractBitsForFixup() 64 case SystemZ::FK_390_PC32DBL: in extractBitsForFixup() 67 case SystemZ::FK_390_TLS_CALL: in extractBitsForFixup() 70 case SystemZ::FK_390_S8Imm: in extractBitsForFixup() 72 case SystemZ::FK_390_S16Imm: in extractBitsForFixup() 74 case SystemZ::FK_390_S20Imm: { in extractBitsForFixup() 82 case SystemZ::FK_390_S32Imm: in extractBitsForFixup() 84 case SystemZ::FK_390_U1Imm: in extractBitsForFixup() [all …]
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| H A D | SystemZMCAsmInfo.cpp | 17 {SystemZ::S_DTPOFF, "DTPOFF"}, {SystemZ::S_GOT, "GOT"}, 18 {SystemZ::S_GOTENT, "GOTENT"}, {SystemZ::S_INDNTPOFF, "INDNTPOFF"}, 19 {SystemZ::S_NTPOFF, "NTPOFF"}, {SystemZ::S_PLT, "PLT"}, 20 {SystemZ::S_TLSGD, "TLSGD"}, {SystemZ::S_TLSLD, "TLSLD"}, 21 {SystemZ::S_TLSLDM, "TLSLDM"}, 65 case SystemZ::S_None: in printSpecifierExpr() 68 case SystemZ::S_RCon: in printSpecifierExpr() 71 case SystemZ::S_VCon: in printSpecifierExpr()
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| H A D | SystemZMCCodeEmitter.cpp | 65 template <SystemZ::FixupKind Kind> 72 template <SystemZ::FixupKind Kind> 91 SystemZ::FK_390_PC16DBL, 2, false); in getPC16DBLEncoding() 97 SystemZ::FK_390_PC32DBL, 2, false); in getPC32DBLEncoding() 103 SystemZ::FK_390_PC16DBL, 2, true); in getPC16DBLTLSEncoding() 109 SystemZ::FK_390_PC32DBL, 2, true); in getPC32DBLTLSEncoding() 115 SystemZ::FK_390_PC12DBL, 1, false); in getPC12DBLBPPEncoding() 121 SystemZ::FK_390_PC16DBL, 4, false); in getPC16DBLBPPEncoding() 127 SystemZ::FK_390_PC24DBL, 3, false); in getPC24DBLBPPEncoding() 165 template <SystemZ::FixupKind Kind> [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 87 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64)); in splitMove() 88 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64)); in splitMove() 145 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); in splitAdjDynAlloc() 161 bool IsHigh = SystemZ::isHighReg(Reg); in expandRIPseudo() 176 bool DestIsHigh = SystemZ::isHighReg(DestReg); in expandRIEPseudo() 177 bool SrcIsHigh = SystemZ::isHighReg(SrcReg); in expandRIEPseudo() 183 SystemZ::LR, 32, MI.getOperand(1).isKill(), in expandRIEPseudo() 199 SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode, in expandRXYPseudo() 210 unsigned Opcode = SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode; in expandLOCPseudo() 235 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32); in expandLoadStackGuard() [all …]
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| H A D | SystemZShortenInst.cpp | 80 (SystemZ::GRH32BitRegClass.contains(Reg) ? SystemZ::subreg_h32 in shortenIIF() 81 : SystemZ::subreg_l32); in shortenIIF() 83 (thisSubRegIdx == SystemZ::subreg_l32 ? SystemZ::subreg_h32 in shortenIIF() 84 : SystemZ::subreg_l32); in shortenIIF() 86 TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass); in shortenIIF() 92 if (SystemZ::isImmLL(Imm)) { in shortenIIF() 97 if (SystemZ::isImmLH(Imm)) { in shortenIIF() 143 if (LiveRegs.available(SystemZ::CC) && shortenOn001(MI, Opcode)) { in shortenOn001AddCC() 145 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in shortenOn001AddCC() 214 case SystemZ::IILF: in processBlock() [all …]
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| H A D | SystemZCallingConv.cpp | 13 const MCPhysReg SystemZ::ELFArgGPRs[SystemZ::ELFNumArgGPRs] = { 14 SystemZ::R2D, SystemZ::R3D, SystemZ::R4D, SystemZ::R5D, SystemZ::R6D 17 const MCPhysReg SystemZ::ELFArgFPRs[SystemZ::ELFNumArgFPRs] = { 18 SystemZ::F0D, SystemZ::F2D, SystemZ::F4D, SystemZ::F6D 22 const MCPhysReg SystemZ::XPLINK64ArgGPRs[SystemZ::XPLINK64NumArgGPRs] = { 23 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D 27 const MCPhysReg SystemZ::XPLINK64ArgFPRs[SystemZ::XPLINK64NumArgFPRs] = { 28 SystemZ::F0D, SystemZ::F2D, SystemZ::F4D, SystemZ::F6D
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| H A D | SystemZAsmPrinter.cpp | 84 SystemZ::S_PLT, Context); in getTLSGetOffset() 167 MCInstBuilder(SystemZ::BCRAsm) in emitCallInformation() 223 case SystemZ::Return: in emitInstruction() 224 LoweredMI = MCInstBuilder(SystemZ::BR) in emitInstruction() 225 .addReg(SystemZ::R14D); in emitInstruction() 228 case SystemZ::Return_XPLINK: in emitInstruction() 229 LoweredMI = MCInstBuilder(SystemZ::B) in emitInstruction() 230 .addReg(SystemZ::R7D) in emitInstruction() 235 case SystemZ::CondReturn: in emitInstruction() 236 LoweredMI = MCInstBuilder(SystemZ::BCR) in emitInstruction() [all …]
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| H A D | SystemZFrameLowering.cpp | 32 { SystemZ::R2D, 0x10 }, 33 { SystemZ::R3D, 0x18 }, 34 { SystemZ::R4D, 0x20 }, 35 { SystemZ::R5D, 0x28 }, 36 { SystemZ::R6D, 0x30 }, 37 { SystemZ::R7D, 0x38 }, 38 { SystemZ::R8D, 0x40 }, 39 { SystemZ::R9D, 0x48 }, 40 { SystemZ::R10D, 0x50 }, 41 { SystemZ::R11D, 0x58 }, [all …]
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| H A D | SystemZLongBranch.cpp | 220 MI.isInlineAsm() || MI.getOpcode() == SystemZ::STACKMAP || in getInstSizeInBytes() 221 MI.getOpcode() == SystemZ::PATCHPOINT || in getInstSizeInBytes() 224 MI.getOpcode() == SystemZ::EH_SjLj_Setup) && in getInstSizeInBytes() 235 case SystemZ::J: in describeTerminator() 239 case SystemZ::BRC: in describeTerminator() 243 case SystemZ::BRCT: in describeTerminator() 244 case SystemZ::BRCTG: in describeTerminator() 248 case SystemZ::BRCTH: in describeTerminator() 252 case SystemZ::CRJ: in describeTerminator() 253 case SystemZ::CLRJ: in describeTerminator() [all …]
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| H A D | SystemZElimCompare.cpp | 109 case SystemZ::LR: in preservesValueOf() 110 case SystemZ::LGR: in preservesValueOf() 111 case SystemZ::LGFR: in preservesValueOf() 112 case SystemZ::LTR: in preservesValueOf() 113 case SystemZ::LTGR: in preservesValueOf() 114 case SystemZ::LTGFR: in preservesValueOf() 158 return (MI.getOpcode() == SystemZ::LTEBR || in isLoadAndTestAsCmp() 159 MI.getOpcode() == SystemZ::LTDBR || in isLoadAndTestAsCmp() 160 MI.getOpcode() == SystemZ::LTXBR) && in isLoadAndTestAsCmp() 186 if (Opcode == SystemZ::AHI) in convertToBRCT() [all …]
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| H A D | SystemZTDC.cpp | 161 SystemZ::TDCMASK_ZERO, // eq in convertFCmp() 162 SystemZ::TDCMASK_POSITIVE, // gt in convertFCmp() 163 SystemZ::TDCMASK_NEGATIVE, // lt in convertFCmp() 164 SystemZ::TDCMASK_NAN, // un in convertFCmp() 167 SystemZ::TDCMASK_INFINITY_PLUS, // eq in convertFCmp() 169 (SystemZ::TDCMASK_ZERO | in convertFCmp() 170 SystemZ::TDCMASK_NEGATIVE | in convertFCmp() 171 SystemZ::TDCMASK_NORMAL_PLUS | in convertFCmp() 172 SystemZ::TDCMASK_SUBNORMAL_PLUS), // lt in convertFCmp() 173 SystemZ::TDCMASK_NAN, // un in convertFCmp() [all …]
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| H A D | SystemZRegisterInfo.cpp | 32 if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) || in getRC32() 33 MO.getSubReg() == SystemZ::subreg_ll32 || in getRC32() 34 MO.getSubReg() == SystemZ::subreg_l32) in getRC32() 35 return &SystemZ::GR32BitRegClass; in getRC32() 36 if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) || in getRC32() 37 MO.getSubReg() == SystemZ::subreg_lh32 || in getRC32() 38 MO.getSubReg() == SystemZ::subreg_h32) in getRC32() 39 return &SystemZ::GRH32BitRegClass; in getRC32() 43 if (SystemZ::GR32BitRegClass.contains(PhysReg)) in getRC32() 44 return &SystemZ::GR32BitRegClass; in getRC32() [all …]
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| H A D | SystemZISelLowering.cpp | 100 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass); in SystemZTargetLowering() 102 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass); in SystemZTargetLowering() 103 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass); in SystemZTargetLowering() 106 addRegisterClass(MVT::f16, &SystemZ::VR16BitRegClass); in SystemZTargetLowering() 107 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass); in SystemZTargetLowering() 108 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass); in SystemZTargetLowering() 110 addRegisterClass(MVT::f16, &SystemZ::FP16BitRegClass); in SystemZTargetLowering() 111 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass); in SystemZTargetLowering() 112 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass); in SystemZTargetLowering() 115 addRegisterClass(MVT::f128, &SystemZ::VR128BitRegClass); in SystemZTargetLowering() [all …]
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| H A D | SystemZRegisterInfo.h | 23 namespace SystemZ { 36 if (SystemZ::GRH32BitRegClass.contains(Reg)) in isHighReg() 38 assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32"); in isHighReg() 84 int getReturnFunctionAddressRegister() final { return SystemZ::R7D; }; in getReturnFunctionAddressRegister() 86 int getStackPointerRegister() final { return SystemZ::R4D; }; in getStackPointerRegister() 88 int getFramePointerRegister() final { return SystemZ::R8D; }; in getFramePointerRegister() 90 int getAddressOfCalleeRegister() { return SystemZ::R6D; }; in getAddressOfCalleeRegister() 92 int getADARegister() { return SystemZ::R5D; } in getADARegister() 111 int getReturnFunctionAddressRegister() final { return SystemZ::R14D; }; in getReturnFunctionAddressRegister() 113 int getStackPointerRegister() final { return SystemZ::R15D; }; in getStackPointerRegister() [all …]
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| H A D | SystemZPostRewrite.cpp | 83 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectLOCRMux() 84 bool SrcIsHigh = SystemZ::isHighReg(SrcReg); in selectLOCRMux() 107 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectSELRMux() 108 bool Src1IsHigh = SystemZ::isHighReg(Src1Reg); in selectSELRMux() 109 bool Src2IsHigh = SystemZ::isHighReg(Src2Reg); in selectSELRMux() 120 TII->get(SystemZ::COPY), DestReg) in selectSELRMux() 133 TII->get(SystemZ::COPY), DestReg) in selectSELRMux() 140 TII->get(SystemZ::COPY), DestReg) in selectSELRMux() 206 BuildMI(&MBB, DL, TII->get(SystemZ::BRC)) in expandCondMove() 214 BuildMI(*MoveMBB, MoveMBB->end(), DL, TII->get(SystemZ::COPY), DestReg) in expandCondMove() [all …]
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| H A D | SystemZCopyPhysRegs.cpp | 77 (SrcReg == SystemZ::CC || SystemZ::AR32BitRegClass.contains(SrcReg))) { in visitMBB() 78 Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass); in visitMBB() 79 if (SrcReg == SystemZ::CC) in visitMBB() 80 BuildMI(MBB, MI, DL, TII->get(SystemZ::IPM), Tmp); in visitMBB() 82 BuildMI(MBB, MI, DL, TII->get(SystemZ::EAR), Tmp).addReg(SrcReg); in visitMBB() 87 SystemZ::AR32BitRegClass.contains(DstReg)) { in visitMBB() 88 Register Tmp = MRI->createVirtualRegister(&SystemZ::GR32BitRegClass); in visitMBB() 91 BuildMI(MBB, MBBI, DL, TII->get(SystemZ::SAR), DstReg).addReg(Tmp); in visitMBB()
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| H A D | SystemZCallingConv.h | 18 namespace SystemZ { 121 Reg = State.AllocateReg(SystemZ::ELFArgGPRs); in CC_SystemZ_I128Indirect() 123 Reg = State.AllocateReg(SystemZ::XPLINK64ArgGPRs); in CC_SystemZ_I128Indirect() 160 State.AllocateReg(SystemZ::XPLINK64ArgGPRs); in CC_XPLINK64_Shadow_Reg() 164 State.AllocateReg(SystemZ::XPLINK64ArgGPRs); in CC_XPLINK64_Shadow_Reg() 165 State.AllocateReg(SystemZ::XPLINK64ArgGPRs); in CC_XPLINK64_Shadow_Reg() 170 for (unsigned I = 0; I < SystemZ::XPLINK64NumArgFPRs; I += 2) in CC_XPLINK64_Shadow_Reg() 171 if (State.isAllocated(SystemZ::XPLINK64ArgFPRs[I])) in CC_XPLINK64_Shadow_Reg() 172 State.AllocateReg(SystemZ::XPLINK64ArgFPRs[I + 1]); in CC_XPLINK64_Shadow_Reg() 189 State.AllocateReg(SystemZ::R1D); in CC_XPLINK64_Allocate128BitVararg() [all …]
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| H A D | SystemZISelDAGToDAG.cpp | 803 if (RxSBG.Opcode == SystemZ::RNSBG) in expandRxSBG() 815 if (RxSBG.Opcode == SystemZ::RNSBG) in expandRxSBG() 838 if (RxSBG.Opcode != SystemZ::RNSBG) in expandRxSBG() 879 if (RxSBG.Opcode != SystemZ::RNSBG) { in expandRxSBG() 918 if (RxSBG.Opcode == SystemZ::RNSBG) { in expandRxSBG() 945 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) { in expandRxSBG() 974 return CurDAG->getTargetInsertSubreg(SystemZ::subreg_l32, in convertTo() 977 return CurDAG->getTargetExtractSubreg(SystemZ::subreg_l32, DL, VT, N); in convertTo() 987 RxSBGOperands RISBG(SystemZ::RISBG, SDValue(N, 0)); in tryRISBGZero() 1027 SystemZ::isImmLF(~RISBG.Mask) || in tryRISBGZero() [all …]
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| H A D | SystemZ.td | 1 //===-- SystemZ.td - Describe the SystemZ target machine -----*- tblgen -*-===// 16 // SystemZ subtarget features 22 // SystemZ subtarget scheduling models 28 // SystemZ supported processors 88 // The SystemZ target supports two different syntaxes for emitting machine code. 102 def SystemZ : Target {
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| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaSystemZ.cpp | 26 if (BuiltinID == SystemZ::BI__builtin_tabort) { in CheckSystemZBuiltinFunctionCall() 40 case SystemZ::BI__builtin_s390_lcbb: i = 1; l = 0; u = 15; break; in CheckSystemZBuiltinFunctionCall() 41 case SystemZ::BI__builtin_s390_veval: in CheckSystemZBuiltinFunctionCall() 42 case SystemZ::BI__builtin_s390_verimb: in CheckSystemZBuiltinFunctionCall() 43 case SystemZ::BI__builtin_s390_verimh: in CheckSystemZBuiltinFunctionCall() 44 case SystemZ::BI__builtin_s390_verimf: in CheckSystemZBuiltinFunctionCall() 45 case SystemZ::BI__builtin_s390_verimg: i = 3; l = 0; u = 255; break; in CheckSystemZBuiltinFunctionCall() 46 case SystemZ::BI__builtin_s390_vfaeb: in CheckSystemZBuiltinFunctionCall() 47 case SystemZ::BI__builtin_s390_vfaeh: in CheckSystemZBuiltinFunctionCall() 48 case SystemZ::BI__builtin_s390_vfaef: in CheckSystemZBuiltinFunctionCall() [all …]
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/ |
| H A D | SystemZ.cpp | 42 case SystemZ::BI__builtin_tbegin: { in EmitSystemZBuiltinExpr() 48 case SystemZ::BI__builtin_tbegin_nofloat: { in EmitSystemZBuiltinExpr() 54 case SystemZ::BI__builtin_tbeginc: { in EmitSystemZBuiltinExpr() 60 case SystemZ::BI__builtin_tabort: { in EmitSystemZBuiltinExpr() 65 case SystemZ::BI__builtin_non_tx_store: { in EmitSystemZBuiltinExpr() 77 case SystemZ::BI__builtin_s390_vclzb: in EmitSystemZBuiltinExpr() 78 case SystemZ::BI__builtin_s390_vclzh: in EmitSystemZBuiltinExpr() 79 case SystemZ::BI__builtin_s390_vclzf: in EmitSystemZBuiltinExpr() 80 case SystemZ::BI__builtin_s390_vclzg: in EmitSystemZBuiltinExpr() 81 case SystemZ::BI__builtin_s390_vclzq: { in EmitSystemZBuiltinExpr() [all …]
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| /freebsd/contrib/llvm-project/lld/ELF/Arch/ |
| H A D | SystemZ.cpp | 23 class SystemZ : public TargetInfo { class 25 SystemZ(Ctx &); 53 SystemZ::SystemZ(Ctx &ctx) : TargetInfo(ctx) { in SystemZ() function in SystemZ 82 RelExpr SystemZ::getRelExpr(RelType type, const Symbol &s, in getRelExpr() 178 void SystemZ::writeGotHeader(uint8_t *buf) const { in writeGotHeader() 184 void SystemZ::writeGotPlt(uint8_t *buf, const Symbol &s) const { in writeGotPlt() 188 void SystemZ::writeIgotPlt(uint8_t *buf, const Symbol &s) const { in writeIgotPlt() 193 void SystemZ::writePltHeader(uint8_t *buf) const { in writePltHeader() 210 void SystemZ::addPltHeaderSymbols(InputSection &isec) const { in addPltHeaderSymbols() 216 void SystemZ::writePlt(uint8_t *buf, const Symbol &sym, in writePlt() [all …]
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