Lines Matching refs:SystemZ

1 //===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
32   if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
33       MO.getSubReg() == SystemZ::subreg_ll32 ||
34       MO.getSubReg() == SystemZ::subreg_l32)
35     return &SystemZ::GR32BitRegClass;
36   if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
37       MO.getSubReg() == SystemZ::subreg_lh32 ||
38       MO.getSubReg() == SystemZ::subreg_h32)
39     return &SystemZ::GRH32BitRegClass;
43     if (SystemZ::GR32BitRegClass.contains(PhysReg))
44       return &SystemZ::GR32BitRegClass;
45     assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
47     return &SystemZ::GRH32BitRegClass;
50   assert (RC == &SystemZ::GRX32BitRegClass);
89       if (SystemZ::getTwoOperandOpcode(Use.getOpcode()) != -1) {
131   if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
145         if (Use.getOpcode() == SystemZ::LOCRMux ||
146             Use.getOpcode() == SystemZ::SELRMux) {
152           if (Use.getOpcode() == SystemZ::SELRMux)
155           if (RC && RC != &SystemZ::GRX32BitRegClass) {
166           if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)
169         else if (Use.getOpcode() == SystemZ::CHIMux ||
170                  Use.getOpcode() == SystemZ::CFIMux) {
174               if (DefMI.getOpcode() != SystemZ::LMux)
177               addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI);
275   Reserved.set(SystemZ::A0);
276   Reserved.set(SystemZ::A1);
279   Reserved.set(SystemZ::FPC);
324     if (OpcodeForOffset == SystemZ::LE &&
327       OpcodeForOffset = SystemZ::LDE32;
344         MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
357       unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
365         BuildMI(MBB, MI, DL, TII->get(SystemZ::LA), ScratchReg)
389   if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
443   if (RC == &SystemZ::CCRRegClass)
444     return &SystemZ::GR32BitRegClass;