| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVSystemOperands.td | 20 class SysReg<string name, bits<12> op> {
42 let FilterClass = "SysReg";
55 let FilterClass = "SysReg";
73 def SysRegFFLAGS : SysReg<"fflags", 0x001>;
74 def SysRegFRM : SysReg<"frm", 0x002>;
75 def SysRegFCSR : SysReg<"fcsr", 0x003>;
80 def : SysReg<"vstart", 0x008>;
81 def : SysReg<"vxsat", 0x009>;
82 def SysRegVXRM : SysReg<"vxrm", 0x00A>;
83 def : SysReg<"vcsr", 0x00F>;
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| H A D | RISCVInstrInfo.td | 1999 class ReadSysReg<SysReg SR, list<Register> Regs>
2007 class WriteSysReg<SysReg SR, list<Register> Regs>
2015 class WriteSysRegImm<SysReg SR, list<Register> Regs>
2023 class SwapSysReg<SysReg SR, list<Register> Regs>
2032 class SwapSysRegImm<SysReg SR, list<Register> Regs>
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 407 SysRegOp SysReg; member
437 SysReg = o.SysReg; in RISCVOperand()
990 return StringRef(SysReg.Data, SysReg.Length); in getSysReg()
1048 OS << "<sysreg: " << getSysReg() << " (" << SysReg.Encoding << ")>"; in print()
1121 Op->SysReg.Data = Str.data(); in createSysReg()
1122 Op->SysReg.Length = Str.size(); in createSysReg()
1123 Op->SysReg.Encoding = Encoding; in createSysReg()
1229 Inst.addOperand(MCOperand::createImm(SysReg.Encoding)); in addCSRSystemRegisterOperands()
1951 const auto *SysReg = RISCVSysReg::lookupSysRegByName(Identifier); in parseCSRSystemRegister() local
1953 if (SysReg) { in parseCSRSystemRegister()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 522 struct SysRegOp SysReg; member
581 SysReg = o.SysReg; in AArch64Operand()
729 return StringRef(SysReg.Data, SysReg.Length); in getSysReg()
1203 return SysReg.MRSReg != -1U; in isMRSSystemRegister()
1208 return SysReg.MSRReg != -1U; in isMSRSystemRegister()
1213 return AArch64PState::lookupPStateImm0_1ByEncoding(SysReg.PStateField); in isSystemPStateFieldWithImm0_1()
1219 return AArch64PState::lookupPStateImm0_15ByEncoding(SysReg.PStateField); in isSystemPStateFieldWithImm0_15()
2147 Inst.addOperand(MCOperand::createImm(SysReg.MRSReg)); in addMRSSystemRegisterOperands()
2153 Inst.addOperand(MCOperand::createImm(SysReg.MSRReg)); in addMSRSystemRegisterOperands()
2159 Inst.addOperand(MCOperand::createImm(SysReg.PStateField)); in addSystemPStateFieldWithImm0_1Operands()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ExpandPseudoInsts.cpp | 1474 auto SysReg = AArch64SysReg::TPIDR_EL0; in expandMI() local
1477 SysReg = AArch64SysReg::TPIDR_EL3; in expandMI()
1479 SysReg = AArch64SysReg::TPIDR_EL2; in expandMI()
1481 SysReg = AArch64SysReg::TPIDR_EL1; in expandMI()
1483 SysReg = AArch64SysReg::TPIDRRO_EL0; in expandMI()
1485 .addImm(SysReg); in expandMI()
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| H A D | AArch64SystemOperands.td | 964 class SysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
979 let FilterClass = "SysReg";
985 let FilterClass = "SysReg";
1000 : SysReg<name, op0, op1, crn, crm, op2> {
1007 : SysReg<name, op0, op1, crn, crm, op2> {
1014 : SysReg<name, op0, op1, crn, crm, op2> {
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| H A D | AArch64InstrInfo.cpp | 2126 const AArch64SysReg::SysReg *SrcReg = in expandPostRAPseudo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVBaseInfo.h | 511 struct SysReg { struct
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 1887 static bool isValidSysReg(const AArch64SysReg::SysReg &Reg, bool Read, in isValidSysReg()
1897 static const AArch64SysReg::SysReg *lookupSysReg(unsigned Val, bool Read, in lookupSysReg()
1927 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, true /*Read*/, STI); in printMRSSystemRegister()
1954 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, false /*Read*/, STI); in printMSRSystemRegister()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 769 struct SysReg { struct
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrVFP.td | 2879 class vfp_vstrldr<bit opc, bit P, bit W, bits<4> SysReg, string sysreg,
2888 let Inst{22} = SysReg{3};
2892 let Inst{15-13} = SysReg{2-0};
2901 multiclass vfp_vstrldr_sysreg<bit opc, bits<4> SysReg, string sysreg,
2904 vfp_vstrldr<opc, 1, 0, SysReg, sysreg,
2911 vfp_vstrldr<opc, 1, 1, SysReg, sysreg,
2919 vfp_vstrldr<opc, 0, 1, SysReg, sysreg,
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/ |
| H A D | ARM.cpp | 2556 StringRef SysReg = "") { in EmitSpecialRegisterBuiltin() argument
2566 if (SysReg.empty()) { in EmitSpecialRegisterBuiltin()
2568 SysReg = cast<clang::StringLiteral>(SysRegStrExpr)->getString(); in EmitSpecialRegisterBuiltin()
2571 llvm::Metadata *Ops[] = { llvm::MDString::get(Context, SysReg) }; in EmitSpecialRegisterBuiltin()
5478 unsigned SysReg = in EmitAArch64BuiltinExpr() local
5484 ? ((1 << 1) | ((SysReg >> 14) & 1)) in EmitAArch64BuiltinExpr()
5487 << SysRegOp0 << ":" << ((SysReg >> 11) & 7) << ":" in EmitAArch64BuiltinExpr()
5488 << ((SysReg >> 7) & 15) << ":" << ((SysReg >> 3) & 15) << ":" in EmitAArch64BuiltinExpr()
5489 << (SysReg & 7); in EmitAArch64BuiltinExpr()
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