Home
last modified time | relevance | path

Searched refs:SubRegs (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRewritePartialRegUses.cpp67 SubRegMap &SubRegs) const;
85 SubRegMap &SubRegs) const;
90 SubRegMap &SubRegs) const;
103 mutable SmallDenseMap<std::pair<unsigned, unsigned>, unsigned> SubRegs; member in __anonf1e524d80111::GCNRewritePartialRegUsesImpl
154 const auto [I, Inserted] = SubRegs.try_emplace({Offset, Size}, 0); in getSubReg()
208 SubRegMap &SubRegs) const { in getRegClassWithShiftedSubregs()
215 for (auto &[OldSubReg, NewSubReg] : SubRegs) { in getRegClassWithShiftedSubregs()
269 for (auto [OldSubReg, NewSubReg] : SubRegs) in getRegClassWithShiftedSubregs()
281 SubRegMap &SubRegs) const { in getMinSizeReg()
285 for (auto [SubReg, SRI] : SubRegs) { in getMinSizeReg()
[all …]
H A DAMDGPUInstructionSelector.cpp654 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8); in selectG_MERGE_VALUES() local
660 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
699 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8); in selectG_UNMERGE_VALUES() local
703 .addReg(SrcReg, 0, SubRegs[I]); in selectG_UNMERGE_VALUES()
706 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]); in selectG_UNMERGE_VALUES()
3220 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize); in computeIndirectRegIndex() local
3224 if (static_cast<unsigned>(Offset) >= SubRegs.size()) in computeIndirectRegIndex()
3225 return std::pair(IdxReg, SubRegs[0]); in computeIndirectRegIndex()
3226 return std::pair(IdxBaseReg, SubRegs[Offset]); in computeIndirectRegIndex()
H A DSIInstrInfo.cpp6364 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32; in readlaneVGPRToSGPR() local
6375 if (SubRegs == 1) { in readlaneVGPRToSGPR()
6383 for (unsigned i = 0; i < SubRegs; ++i) { in readlaneVGPRToSGPR()
6394 for (unsigned i = 0; i < SubRegs; ++i) { in readlaneVGPRToSGPR()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfoDMR.td46 let SubRegs = subregs;
53 let SubRegs = subregs;
61 let SubRegs = subregs;
66 let SubRegs = subregs;
71 let SubRegs = subregs;
H A DPPCRegisterInfoMMA.td22 let SubRegs = subregs;
31 let SubRegs = subregs;
H A DPPCRegisterInfo.td44 let SubRegs = [SubReg];
50 let SubRegs = subregs;
68 let SubRegs = [!cast<FPR>("F"#EvenIndex), !cast<FPR>("F"#!add(EvenIndex, 1))];
84 let SubRegs = [SubReg, SubRegH];
92 let SubRegs = [SubReg, SubRegH];
105 let SubRegs = subregs;
116 let SubRegs = subregs;
123 let SubRegs = [!cast<GP8>("X"#EvenIndex), !cast<GP8>("X"#!add(EvenIndex, 1))];
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp207 for (const auto &[_, SR] : SubRegs) { in inheritRegUnits()
219 return SubRegs; in computeSubRegs()
228 if (!SubRegs.try_emplace(Idx, SR).second) in computeSubRegs()
247 if (!SubRegs.insert(SR).second) in computeSubRegs()
260 CodeGenRegister *SR = SubRegs[Idx]; in computeSubRegs()
271 if (SubRegs.count(Val) || !Orphans.erase(SRI->second)) in computeSubRegs()
274 SubRegs.try_emplace(Val, SRI->second); in computeSubRegs()
297 CodeGenRegister *SR = SubRegs[Idx]; in computeSubRegs()
301 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SRI)] = SubReg; in computeSubRegs()
305 for (auto &[SRI, SubReg] : SubRegs) { in computeSubRegs()
[all …]
H A DCodeGenRegisters.h210 return SubRegs; in getSubRegs()
301 SubRegMap SubRegs; variable
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.td19 let SubRegs = subregs;
35 let SubRegs = subregs;
45 let SubRegs = subregs;
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td17 let SubRegs = subregs;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td34 let SubRegs = [subreg];
42 let SubRegs = [subreg];
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h116 uint32_t SubRegs; // Sub-register set, described above member
535 I.init(Reg.id(), MCRI->DiffLists + MCRI->get(Reg).SubRegs);
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td42 let SubRegs = subregs;
51 let SubRegs = subregs;
58 let SubRegs = subregs;
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td66 let SubRegs = subregs;
87 let SubRegs = subregs;
99 let SubRegs = subregs;
115 let SubRegs = subregs;
169 let SubRegs = [USR_OVF];
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td132 // in the SubRegs field of a Register definition. For example:
178 // SubRegs - A list of registers that are parts of this register. Note these
180 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
182 list<Register> SubRegs = [];
184 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
186 // SubRegs.
239 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
243 let SubRegs = subregs;
435 // SubRegs - N lists of registers to be zipped up. Super-registers are
436 // synthesized from the first element of each SubRegs list, the second
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.td22 let SubRegs = SUBREGS;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp763 unsigned SubRegs = 0; in copyPhysReg() local
770 SubRegs = 2; in copyPhysReg()
774 SubRegs = 4; in copyPhysReg()
779 SubRegs = 2; in copyPhysReg()
783 SubRegs = 3; in copyPhysReg()
787 SubRegs = 4; in copyPhysReg()
791 SubRegs = 2; in copyPhysReg()
795 SubRegs = 2; in copyPhysReg()
800 SubRegs = 3; in copyPhysReg()
805 SubRegs = 4; in copyPhysReg()
[all …]
H A DARMISelDAGToDAG.cpp2929 uint16_t SubRegs[2] = {ARM::gsub_0, ARM::gsub_1}; in SelectCDE_CXxD() local
2931 std::swap(SubRegs[0], SubRegs[1]); in SelectCDE_CXxD()
2936 SDValue SubReg = CurDAG->getTargetExtractSubreg(SubRegs[ResIdx], Loc, in SelectCDE_CXxD()
H A DARMRegisterInfo.td20 let SubRegs = subregs;
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td20 let SubRegs = subregs;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp358 const unsigned SubRegs[]);
1404 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, in createDTuple() local
1407 return createTuple(Regs, RegClassIDs, SubRegs); in createDTuple()
1413 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1, in createQTuple() local
1416 return createTuple(Regs, RegClassIDs, SubRegs); in createQTuple()
1423 static const unsigned SubRegs[] = {AArch64::zsub0, AArch64::zsub1, in createZTuple() local
1426 return createTuple(Regs, RegClassIDs, SubRegs); in createZTuple()
1436 static const unsigned SubRegs[] = {AArch64::zsub0, AArch64::zsub1, in createZMulTuple() local
1438 return createTuple(Regs, RegClassIDs, SubRegs); in createZMulTuple()
1443 const unsigned SubRegs[]) { in createTuple() argument
[all …]
H A DAArch64RegisterInfo.td18 let SubRegs = subregs;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp712 const unsigned SubRegs[], MachineIRBuilder &MIB) { in createTuple() argument
724 RegSequence.addImm(SubRegs[I]); in createTuple()
733 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, in createDTuple() local
735 return createTuple(Regs, RegClassIDs, SubRegs, MIB); in createDTuple()
742 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1, in createQTuple() local
744 return createTuple(Regs, RegClassIDs, SubRegs, MIB); in createQTuple()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td18 let SubRegs = subregs;