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Searched refs:SubRegs (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRewritePartialRegUses.cpp98 SubRegMap &SubRegs) const;
118 SubRegMap &SubRegs) const;
123 SubRegMap &SubRegs) const;
139 mutable SmallDenseMap<std::pair<unsigned, unsigned>, unsigned> SubRegs; member in __anonf1e524d80111::GCNRewritePartialRegUses
167 const auto [I, Inserted] = SubRegs.try_emplace({Offset, Size}, 0); in getSubReg()
221 unsigned CoverSubregIdx, SubRegMap &SubRegs) const { in getRegClassWithShiftedSubregs()
228 for (auto &[OldSubReg, SRI] : SubRegs) { in getRegClassWithShiftedSubregs()
283 for (auto [SubReg, SRI] : SubRegs) in getRegClassWithShiftedSubregs()
295 SubRegMap &SubRegs) const { in getMinSizeReg()
299 for (auto [SubReg, SRI] : SubRegs) { in getMinSizeReg()
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H A DAMDGPUInstructionSelector.cpp556 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8); in selectG_MERGE_VALUES() local
562 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
601 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8); in selectG_UNMERGE_VALUES() local
605 .addReg(SrcReg, 0, SubRegs[I]); in selectG_UNMERGE_VALUES()
608 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]); in selectG_UNMERGE_VALUES()
3026 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize); in computeIndirectRegIndex() local
3030 if (static_cast<unsigned>(Offset) >= SubRegs.size()) in computeIndirectRegIndex()
3031 return std::pair(IdxReg, SubRegs[0]); in computeIndirectRegIndex()
3032 return std::pair(IdxBaseReg, SubRegs[Offset]); in computeIndirectRegIndex()
H A DSIInstrInfo.cpp6062 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32; in readlaneVGPRToSGPR() local
6073 if (SubRegs == 1) { in readlaneVGPRToSGPR()
6081 for (unsigned i = 0; i < SubRegs; ++i) { in readlaneVGPRToSGPR()
6092 for (unsigned i = 0; i < SubRegs; ++i) { in readlaneVGPRToSGPR()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfoDMR.td46 let SubRegs = subregs;
53 let SubRegs = subregs;
61 let SubRegs = subregs;
66 let SubRegs = subregs;
71 let SubRegs = subregs;
H A DPPCRegisterInfoMMA.td22 let SubRegs = subregs;
31 let SubRegs = subregs;
H A DPPCRegisterInfo.td44 let SubRegs = [SubReg];
50 let SubRegs = subregs;
68 let SubRegs = [!cast<FPR>("F"#EvenIndex), !cast<FPR>("F"#!add(EvenIndex, 1))];
84 let SubRegs = [SubReg, SubRegH];
92 let SubRegs = [SubReg, SubRegH];
105 let SubRegs = subregs;
116 let SubRegs = subregs;
123 let SubRegs = [!cast<GP8>("X"#EvenIndex), !cast<GP8>("X"#!add(EvenIndex, 1))];
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.cpp266 for (const auto &SubReg : SubRegs) { in inheritRegUnits()
279 return SubRegs; in computeSubRegs()
290 if (!SubRegs.insert(std::pair(Idx, SR)).second) in computeSubRegs()
309 if (!SubRegs.insert(SR).second) in computeSubRegs()
322 CodeGenRegister *SR = SubRegs[Idx]; in computeSubRegs()
333 if (SubRegs.count(Comp.second) || !Orphans.erase(SRI->second)) in computeSubRegs()
336 SubRegs.insert(std::pair(Comp.second, SRI->second)); in computeSubRegs()
359 CodeGenRegister *SR = SubRegs[Idx]; in computeSubRegs()
363 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SubReg.first)] = in computeSubRegs()
368 for (const auto &SubReg : SubRegs) { in computeSubRegs()
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H A DCodeGenRegisters.h208 return SubRegs; in getSubRegs()
299 SubRegMap SubRegs; variable
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.td19 let SubRegs = subregs;
35 let SubRegs = subregs;
45 let SubRegs = subregs;
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td17 let SubRegs = subregs;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td34 let SubRegs = [subreg];
42 let SubRegs = [subreg];
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h115 uint32_t SubRegs; // Sub-register set, described above member
519 I.init(Reg.id(), MCRI->DiffLists + MCRI->get(Reg).SubRegs);
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td42 let SubRegs = subregs;
51 let SubRegs = subregs;
58 let SubRegs = subregs;
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td66 let SubRegs = subregs;
87 let SubRegs = subregs;
99 let SubRegs = subregs;
115 let SubRegs = subregs;
169 let SubRegs = [USR_OVF];
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.td22 let SubRegs = SUBREGS;
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td127 // in the SubRegs field of a Register definition. For example:
173 // SubRegs - A list of registers that are parts of this register. Note these
175 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
177 list<Register> SubRegs = [];
179 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
181 // SubRegs.
234 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
238 let SubRegs = subregs;
430 // SubRegs - N lists of registers to be zipped up. Super-registers are
431 // synthesized from the first element of each SubRegs list, the second
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp936 unsigned SubRegs = 0; in copyPhysReg() local
943 SubRegs = 2; in copyPhysReg()
947 SubRegs = 4; in copyPhysReg()
952 SubRegs = 2; in copyPhysReg()
956 SubRegs = 3; in copyPhysReg()
960 SubRegs = 4; in copyPhysReg()
964 SubRegs = 2; in copyPhysReg()
968 SubRegs = 2; in copyPhysReg()
973 SubRegs = 3; in copyPhysReg()
978 SubRegs = 4; in copyPhysReg()
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H A DARMRegisterInfo.td20 let SubRegs = subregs;
H A DARMISelDAGToDAG.cpp2938 uint16_t SubRegs[2] = {ARM::gsub_0, ARM::gsub_1}; in SelectCDE_CXxD() local
2940 std::swap(SubRegs[0], SubRegs[1]); in SelectCDE_CXxD()
2945 SDValue SubReg = CurDAG->getTargetExtractSubreg(SubRegs[ResIdx], Loc, in SelectCDE_CXxD()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td20 let SubRegs = subregs;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp363 const unsigned SubRegs[]);
1400 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, in createDTuple() local
1403 return createTuple(Regs, RegClassIDs, SubRegs); in createDTuple()
1409 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1, in createQTuple() local
1412 return createTuple(Regs, RegClassIDs, SubRegs); in createQTuple()
1419 static const unsigned SubRegs[] = {AArch64::zsub0, AArch64::zsub1, in createZTuple() local
1422 return createTuple(Regs, RegClassIDs, SubRegs); in createZTuple()
1432 static const unsigned SubRegs[] = {AArch64::zsub0, AArch64::zsub1, in createZMulTuple() local
1434 return createTuple(Regs, RegClassIDs, SubRegs); in createZMulTuple()
1439 const unsigned SubRegs[]) { in createTuple() argument
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H A DAArch64RegisterInfo.td18 let SubRegs = subregs;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp705 const unsigned SubRegs[], MachineIRBuilder &MIB) { in createTuple() argument
717 RegSequence.addImm(SubRegs[I]); in createTuple()
726 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, in createDTuple() local
728 return createTuple(Regs, RegClassIDs, SubRegs, MIB); in createDTuple()
735 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1, in createQTuple() local
737 return createTuple(Regs, RegClassIDs, SubRegs, MIB); in createQTuple()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td18 let SubRegs = subregs;