Searched refs:SubRegRC (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRewritePartialRegUses.cpp | 229 auto &[SubRegRC, NewSubReg] = SRI; in getRegClassWithShiftedSubregs()
230 assert(SubRegRC); in getRegClassWithShiftedSubregs()
233 << TRI->getRegClassName(SubRegRC) in getRegClassWithShiftedSubregs()
234 << (SubRegRC->isAllocatable() ? "" : " not alloc") in getRegClassWithShiftedSubregs()
239 assert(SubRegRC->isAllocatable()); in getRegClassWithShiftedSubregs()
251 const uint32_t *Mask = NewSubReg ? getSuperRegClassMask(SubRegRC, NewSubReg) in getRegClassWithShiftedSubregs()
252 : SubRegRC->getSubClassMask(); in getRegClassWithShiftedSubregs()
431 const TargetRegisterClass *&SubRegRC = I->second.RC; in rewriteReg() local
434 SubRegRC = TRI->getSubRegisterClass(RC, SubReg); in rewriteReg()
436 if (SubRegRC) { in rewriteReg()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.cpp | 1111 CodeGenRegisterClass *SubRegRC = nullptr; in getMatchingSubClassWithSubRegs() local
1116 SubRegRC = SuperRegClassPair.first; in getMatchingSubClassWithSubRegs()
1128 if (SuperRegRC->getMembers().size() >= SubRegRC->getMembers().size()) in getMatchingSubClassWithSubRegs()
1129 return std::pair(ChosenSuperRegClass, SubRegRC); in getMatchingSubClassWithSubRegs()
1136 return std::pair(ChosenSuperRegClass, SubRegRC); in getMatchingSubClassWithSubRegs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 1050 const TargetRegisterClass *SubRegRC = in selectCopy() local
1052 getSubRegForClass(SubRegRC, TRI, SubReg); in selectCopy()
2972 auto SubRegRC = getRegClassForTypeOnBank(MRI.getType(OldDst), RB); in select() local
2973 RBI.constrainGenericRegister(OldDst, *SubRegRC, MRI); in select()
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