229     auto &[SubRegRC, NewSubReg] = SRI;  in getRegClassWithShiftedSubregs()
230     assert(SubRegRC);  in getRegClassWithShiftedSubregs()
233                       << TRI->getRegClassName(SubRegRC)  in getRegClassWithShiftedSubregs()
234                       << (SubRegRC->isAllocatable() ? "" : " not alloc")  in getRegClassWithShiftedSubregs()
239       assert(SubRegRC->isAllocatable());  in getRegClassWithShiftedSubregs()
251     const uint32_t *Mask = NewSubReg ? getSuperRegClassMask(SubRegRC, NewSubReg)  in getRegClassWithShiftedSubregs()
252                                      : SubRegRC->getSubClassMask();  in getRegClassWithShiftedSubregs()
431     const TargetRegisterClass *&SubRegRC = I->second.RC;  in rewriteReg()  local
434       SubRegRC = TRI->getSubRegisterClass(RC, SubReg);  in rewriteReg()
436     if (SubRegRC) {  in rewriteReg()
438         LLVM_DEBUG(dbgs() << TRI->getRegClassName(SubRegRC) << " & "  in rewriteReg()
440         SubRegRC = TRI->getCommonSubClass(SubRegRC, OpDescRC);  in rewriteReg()
444     if (!SubRegRC) {  in rewriteReg()
448     LLVM_DEBUG(dbgs() << TRI->getRegClassName(SubRegRC) << '\n');  in rewriteReg()