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Searched refs:SrcVT (Results 1 – 25 of 50) sorted by relevance

12

/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp167 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
824 MVT SrcVT = SrcEVT.getSimpleVT(); in PPCEmitCmp() local
826 if (SrcVT == MVT::i1 && Subtarget->useCRBits()) in PPCEmitCmp()
840 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || in PPCEmitCmp()
841 SrcVT == MVT::i8 || SrcVT == MVT::i1) { in PPCEmitCmp()
867 switch (SrcVT.SimpleTy) { in PPCEmitCmp()
932 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
938 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
957 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in SelectFPExt() local
960 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in SelectFPExt()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp183 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
184 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
187 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
189 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
190 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
192 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
991 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPExt() local
994 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in selectFPExt()
1070 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPTrunc() local
1073 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in selectFPTrunc()
[all …]
H A DMipsMSAInstrInfo.td3589 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3591 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3592 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3646 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3649 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3650 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3654 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3657 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3658 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3662 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp199 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
234 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
259 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
262 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
265 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, uint64_t Imm,
1188 MVT SrcVT = RetVT; in emitAddSub() local
1214 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1294 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
2835 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true); in selectFPToInt() local
2836 if (SrcVT == MVT::f128 || SrcVT == MVT::f16 || SrcVT == MVT::bf16) in selectFPToInt()
[all …]
H A DAArch64ISelLowering.cpp4291 EVT SrcVT = SrcVal.getValueType(); in LowerFP_ROUND() local
4294 if (useSVEForFixedLengthVectorVT(SrcVT, !Subtarget->isNeonAvailable())) in LowerFP_ROUND()
4305 EVT I32 = SrcVT.changeElementType(MVT::i32); in LowerFP_ROUND()
4306 EVT F32 = SrcVT.changeElementType(MVT::f32); in LowerFP_ROUND()
4307 if (SrcVT.getScalarType() == MVT::f32) { in LowerFP_ROUND()
4315 } else if (SrcVT.getScalarType() == MVT::f64) { in LowerFP_ROUND()
4335 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), SrcVT), in LowerFP_ROUND()
4354 if (SrcVT != MVT::f128) { in LowerFP_ROUND()
4356 if (useSVEForFixedLengthVectorVT(SrcVT)) in LowerFP_ROUND()
4492 EVT SrcVT = SrcVal.getValueType(); in LowerVectorFP_TO_INT_SAT() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp1225 EVT SrcVT = Src.getValueType(); in ExpandANY_EXTEND_VECTOR_INREG() local
1226 int NumSrcElements = SrcVT.getVectorNumElements(); in ExpandANY_EXTEND_VECTOR_INREG()
1230 if (SrcVT.bitsLE(VT)) { in ExpandANY_EXTEND_VECTOR_INREG()
1231 assert((VT.getSizeInBits() % SrcVT.getScalarSizeInBits()) == 0 && in ExpandANY_EXTEND_VECTOR_INREG()
1233 NumSrcElements = VT.getSizeInBits() / SrcVT.getScalarSizeInBits(); in ExpandANY_EXTEND_VECTOR_INREG()
1234 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getScalarType(), in ExpandANY_EXTEND_VECTOR_INREG()
1236 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandANY_EXTEND_VECTOR_INREG()
1252 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask)); in ExpandANY_EXTEND_VECTOR_INREG()
1259 EVT SrcVT = Src.getValueType(); in ExpandSIGN_EXTEND_VECTOR_INREG() local
1269 unsigned SrcEltWidth = SrcVT.getScalarSizeInBits(); in ExpandSIGN_EXTEND_VECTOR_INREG()
[all …]
H A DTargetLowering.cpp697 EVT SrcVT = Src.getValueType(); in SimplifyMultipleUseDemandedBits() local
699 if (SrcVT == DstVT) in SimplifyMultipleUseDemandedBits()
702 unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits(); in SimplifyMultipleUseDemandedBits()
709 if (SrcVT.isVector() && (NumDstEltBits % NumSrcEltBits) == 0) { in SimplifyMultipleUseDemandedBits()
711 unsigned NumSrcElts = SrcVT.getVectorNumElements(); in SimplifyMultipleUseDemandedBits()
734 unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; in SimplifyMultipleUseDemandedBits()
855 EVT SrcVT = Src.getValueType(); in SimplifyMultipleUseDemandedBits() local
858 DstVT.getSizeInBits() == SrcVT.getSizeInBits() && in SimplifyMultipleUseDemandedBits()
859 DemandedBits.getActiveBits() <= SrcVT.getScalarSizeInBits()) { in SimplifyMultipleUseDemandedBits()
2425 EVT SrcVT = Src.getValueType(); in SimplifyDemandedBits() local
[all …]
H A DLegalizeDAG.cpp714 EVT SrcVT = LD->getMemoryVT(); in LegalizeLoadOps() local
715 TypeSize SrcWidth = SrcVT.getSizeInBits(); in LegalizeLoadOps()
719 if (SrcWidth != SrcVT.getStoreSizeInBits() && in LegalizeLoadOps()
727 (SrcVT != MVT::i1 || in LegalizeLoadOps()
732 unsigned NewWidth = SrcVT.getStoreSizeInBits(); in LegalizeLoadOps()
752 Result, DAG.getValueType(SrcVT)); in LegalizeLoadOps()
757 DAG.getValueType(SrcVT)); in LegalizeLoadOps()
763 assert(!SrcVT.isVector() && "Unsupported extload!"); in LegalizeLoadOps()
842 SrcVT.getSimpleVT())) { in LegalizeLoadOps()
870 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) { in LegalizeLoadOps()
[all …]
H A DFastISel.cpp1502 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); in selectCast() local
1505 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1515 if (!TLI.isTypeLegal(SrcVT)) in selectCast()
1523 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1540 MVT SrcVT = SrcEVT.getSimpleVT(); in selectBitCast() local
1547 if (SrcVT == DstVT) { in selectBitCast()
1553 Register ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0); in selectBitCast()
1907 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); in selectOperator() local
1909 if (DstVT.bitsGT(SrcVT)) in selectOperator()
1911 if (DstVT.bitsLT(SrcVT)) in selectOperator()
H A DDAGCombiner.cpp3710 static SDValue getTruncatedUSUBSAT(EVT DstVT, EVT SrcVT, SDValue LHS, in getTruncatedUSUBSAT() argument
3713 assert(DstVT.getScalarSizeInBits() <= SrcVT.getScalarSizeInBits() && in getTruncatedUSUBSAT()
3716 if (DstVT == SrcVT) in getTruncatedUSUBSAT()
3721 APInt UpperBits = APInt::getBitsSetFrom(SrcVT.getScalarSizeInBits(), in getTruncatedUSUBSAT()
3727 DAG.getConstant(APInt::getLowBitsSet(SrcVT.getScalarSizeInBits(), in getTruncatedUSUBSAT()
3729 DL, SrcVT); in getTruncatedUSUBSAT()
3730 RHS = DAG.getNode(ISD::UMIN, DL, SrcVT, RHS, SatLimit); in getTruncatedUSUBSAT()
6792 EVT SrcVT = Src.getValueType(); in combineShiftAnd1ToBitTest() local
6794 if (!TLI.isTypeLegal(SrcVT)) in combineShiftAnd1ToBitTest()
6798 unsigned BitWidth = SrcVT.getScalarSizeInBits(); in combineShiftAnd1ToBitTest()
[all …]
H A DLegalizeVectorTypes.cpp657 EVT SrcVT = Src.getValueType(); in ScalarizeVecRes_FP_TO_XINT_SAT()
661 if (getTypeAction(SrcVT) == TargetLowering::TypeScalarizeVector) in ScalarizeVecRes_FP_TO_XINT_SAT()
665 ISD::EXTRACT_VECTOR_ELT, dl, SrcVT.getVectorElementType(), Src, in ScalarizeVecRes_FP_TO_XINT_SAT()
2562 EVT SrcVT = N->getOperand(0).getValueType(); in SplitVecRes_ExtendOp()
2580 if (SrcVT.getVectorElementCount().isKnownEven() && in SplitVecRes_ExtendOp()
2581 SrcVT.getScalarSizeInBits() * 2 < DestVT.getScalarSizeInBits()) { in SplitVecRes_ExtendOp()
2583 EVT NewSrcVT = SrcVT.widenIntegerVectorElementType(Ctx); in SplitVecRes_ExtendOp()
2584 EVT SplitSrcVT = SrcVT.getHalfNumVectorElementsVT(Ctx); in SplitVecRes_ExtendOp()
2588 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) && in SplitVecRes_ExtendOp()
3007 EVT SrcVT in SplitVecRes_FP_TO_XINT_SAT()
653 EVT SrcVT = Src.getValueType(); ScalarizeVecRes_FP_TO_XINT_SAT() local
2558 EVT SrcVT = N->getOperand(0).getValueType(); SplitVecRes_ExtendOp() local
3003 EVT SrcVT = N->getOperand(0).getValueType(); SplitVecRes_FP_TO_XINT_SAT() local
5124 EVT SrcVT = Src.getValueType(); WidenVecRes_FP_TO_XINT_SAT() local
5145 EVT SrcVT = Src.getValueType(); WidenVecRes_XRINT() local
6684 EVT SrcVT = Src.getValueType(); WidenVecOp_FP_TO_XINT_SAT() local
7273 EVT SrcVT = Source.getValueType(); WidenVecOp_VP_CttzElements() local
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp200 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1342 MVT SrcVT = SrcEVT.getSimpleVT(); in ARMEmitCmp() local
1358 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || in ARMEmitCmp()
1359 SrcVT == MVT::i1) { in ARMEmitCmp()
1373 if (SrcVT == MVT::f32 || SrcVT == MVT::f64) in ARMEmitCmp()
1381 switch (SrcVT.SimpleTy) { in ARMEmitCmp()
1423 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); in ARMEmitCmp()
1426 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1537 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP() local
1538 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in SelectIToFP()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp86 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
700 unsigned Src, EVT SrcVT, in X86FastEmitExtend() argument
702 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); in X86FastEmitExtend()
1245 EVT SrcVT = TLI.getValueType(DL, RV->getType()); in X86SelectRet() local
1248 if (SrcVT != DstVT) { in X86SelectRet()
1249 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) in X86SelectRet()
1255 if (SrcVT == MVT::i1) { in X86SelectRet()
1259 SrcVT = MVT::i8; in X86SelectRet()
1261 if (SrcVT != DstVT) { in X86SelectRet()
1265 fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg); in X86SelectRet()
[all …]
H A DX86ISelLowering.cpp3195 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
3203 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) && in isExtractSubvectorCheap()
5002 EVT SrcVT = Op.getOperand(0).getValueType(); in getTargetConstantBitsFromNode() local
5003 unsigned NumSrcElts = SrcVT.getVectorNumElements(); in getTargetConstantBitsFromNode()
6055 EVT SrcVT = SrcVec.getValueType(); in getFauxShuffleMask() local
6056 if (!SrcVT.getScalarType().isByteSized()) in getFauxShuffleMask()
6059 unsigned SrcByte = SrcIdx * (SrcVT.getScalarSizeInBits() / 8); in getFauxShuffleMask()
6062 std::min<unsigned>(MinBitsPerElt, SrcVT.getScalarSizeInBits()); in getFauxShuffleMask()
6153 EVT SrcVT = Src.getValueType(); in getFauxShuffleMask() local
6155 if (!SrcVT.isSimple() || (SrcVT.getSizeInBits() % 128) != 0 || in getFauxShuffleMask()
[all …]
H A DX86SelectionDAGInfo.cpp252 EVT SrcVT = Src.getValueType(); in emitConstantSizeRepmov() local
256 DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, dl, SrcVT)), in emitConstantSizeRepmov()
H A DX86ISelLowering.h1385 bool isNarrowingProfitable(EVT SrcVT, EVT DestVT) const override;
1449 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
1518 std::pair<SDValue, SDValue> BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL,
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTypePromotion.cpp940 EVT SrcVT = TLI->getValueType(DL, I->getType()); in run() local
941 if (SrcVT.isSimple() && TLI->isTypeLegal(SrcVT.getSimpleVT())) in run()
944 if (TLI->getTypeAction(*Ctx, SrcVT) != TargetLowering::TypePromoteInteger) in run()
947 EVT PromotedVT = TLI->getTypeToTransformTo(*Ctx, SrcVT); in run()
948 if (TLI->isSExtCheaperThanZExt(SrcVT, PromotedVT)) in run()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td319 class isIntType<ValueType SrcVT> {
320 bit ret = !and(SrcVT.isInteger, !ne(SrcVT.Value, i1.Value));
1627 class isModifierType<ValueType SrcVT> {
1628 bit ret = !or(!eq(SrcVT.Value, f16.Value),
1629 !eq(SrcVT.Value, bf16.Value),
1630 !eq(SrcVT.Value, f32.Value),
1631 !eq(SrcVT.Value, f64.Value),
1632 !eq(SrcVT.Value, v2f16.Value),
1633 !eq(SrcVT.Value, v2i16.Value),
1634 !eq(SrcVT.Value, v2bf16.Value),
[all …]
H A DAMDGPUISelLowering.cpp1019 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { in isNarrowingProfitable() argument
1026 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32; in isNarrowingProfitable()
1548 EVT SrcVT = Op.getOperand(0).getValueType(); in LowerEXTRACT_SUBVECTOR() local
1552 unsigned NumSrcElt = SrcVT.getVectorNumElements(); in LowerEXTRACT_SUBVECTOR()
3356 EVT SrcVT = Src.getValueType(); in LowerUINT_TO_FP() local
3358 if (SrcVT == MVT::i16) { in LowerUINT_TO_FP()
3375 if (SrcVT != MVT::i64) in LowerUINT_TO_FP()
3402 EVT SrcVT = Src.getValueType(); in LowerSINT_TO_FP() local
3404 if (SrcVT == MVT::i16) { in LowerSINT_TO_FP()
3421 if (SrcVT != MVT::i64) in LowerSINT_TO_FP()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp1950 EVT SrcVT = Src.getValueType(); in LowerEXTEND_VECTOR_INREG() local
1952 if (SrcVT.getVectorElementType() == MVT::i1 || in LowerEXTEND_VECTOR_INREG()
1953 SrcVT.getVectorElementType() == MVT::i64) in LowerEXTEND_VECTOR_INREG()
1956 assert(VT.getScalarSizeInBits() % SrcVT.getScalarSizeInBits() == 0 && in LowerEXTEND_VECTOR_INREG()
1958 unsigned Scale = VT.getScalarSizeInBits() / SrcVT.getScalarSizeInBits(); in LowerEXTEND_VECTOR_INREG()
2727 EVT SrcVT = In.getValueType(); in truncateVectorWithNARROW() local
2730 if (SrcVT == DstVT) in truncateVectorWithNARROW()
2733 unsigned SrcSizeInBits = SrcVT.getSizeInBits(); in truncateVectorWithNARROW()
2734 unsigned NumElems = SrcVT.getVectorNumElements(); in truncateVectorWithNARROW()
2741 EVT PackedSVT = EVT::getIntegerVT(Ctx, SrcVT.getScalarSizeInBits() / 2); in truncateVectorWithNARROW()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1888 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { in isTruncateFree()
1891 if (SrcVT.isVector() || DstVT.isVector() || !SrcVT.isInteger() || in isTruncateFree()
1894 unsigned SrcBits = SrcVT.getSizeInBits(); in isTruncateFree()
1900 EVT SrcVT = Val.getValueType(); in isTruncateFree()
1904 SrcVT.isVector() && VT2.isVector()) { in isTruncateFree()
1905 unsigned SrcBits = SrcVT.getVectorElementType().getSizeInBits(); in isTruncateFree()
1929 bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const { in isSExtCheaperThanZExt()
1930 return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64; in isSExtCheaperThanZExt()
2292 bool RISCVTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap()
1887 isTruncateFree(EVT SrcVT,EVT DstVT) const isTruncateFree() argument
1899 EVT SrcVT = Val.getValueType(); isTruncateFree() local
1928 isSExtCheaperThanZExt(EVT SrcVT,EVT DstVT) const isSExtCheaperThanZExt() argument
2291 isExtractSubvectorCheap(EVT ResVT,EVT SrcVT,unsigned Index) const isExtractSubvectorCheap() argument
2949 MVT SrcVT = Src.getSimpleValueType(); lowerFP_TO_INT_SAT() local
4669 MVT SrcVT = Src.getSimpleValueType(); lowerVECTOR_SHUFFLEAsVSlidedown() local
5523 MVT SrcVT = Source.getSimpleValueType(); lowerVPCttzElements() local
6578 MVT SrcVT = Src.getSimpleValueType(); LowerOperation() local
8248 MVT SrcVT = Src.getSimpleValueType(); lowerVectorTruncLike() local
8298 MVT SrcVT = Src.getSimpleValueType(); lowerStrictFPExtendOrRoundLike() local
8356 MVT SrcVT = Src.getSimpleValueType(); lowerVectorFPExtendOrRoundLike() local
11302 MVT SrcVT = MVT::getVectorVT(MVT::i1, ContainerVT.getVectorElementCount()); lowerVPExtMaskOp() local
11413 MVT SrcVT = Src.getSimpleValueType(); lowerVPFPIntConvOp() local
13371 EVT SrcVT = Src0.getValueType(); combineBinOpOfZExt() local
13601 EVT SrcVT = N0.getValueType(); combineTruncSelectToSMaxUSat() local
14148 EVT SrcVT = Src.getValueType(); narrowIndex() local
15312 MVT SrcVT = Src.getSimpleValueType(); performFP_TO_INTCombine() local
17487 EVT SrcVT = Src.getOperand(0).getValueType(); PerformDAGCombine() local
17610 EVT SrcVT = N0.getValueType(); PerformDAGCombine() local
[all...]
H A DRISCVISelLowering.h499 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
502 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
526 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2734 static unsigned decideComp(EVT SrcVT, ISD::CondCode CC) { in decideComp() argument
2735 if (SrcVT.isFloatingPoint()) { in decideComp()
2736 if (SrcVT == MVT::f128) in decideComp()
2743 static EVT decideCompType(EVT SrcVT) { in decideCompType() argument
2744 if (SrcVT == MVT::f128) in decideCompType()
2746 return SrcVT; in decideCompType()
2749 static bool safeWithoutCompWithNull(EVT SrcVT, ISD::CondCode CC, in safeWithoutCompWithNull() argument
2751 if (SrcVT.isFloatingPoint()) { in safeWithoutCompWithNull()
2756 return SrcVT != MVT::f128; in safeWithoutCompWithNull()
2771 return isSignedIntSetCC(CC) && SrcVT == MVT::i64; in safeWithoutCompWithNull()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3177 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument
3178 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && in isFPExtFree()
3195 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument
3196 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && in isFPExtFoldable()
3198 return isFPExtFree(DestVT, SrcVT); in isFPExtFoldable()
3293 virtual bool isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { in isNarrowingProfitable() argument
3319 virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h241 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;

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