Home
last modified time | relevance | path

Searched refs:SrcVT (Results 1 – 25 of 54) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp159 bool PPCEmitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT, Register DestReg,
812 MVT SrcVT = SrcEVT.getSimpleVT(); in PPCEmitCmp() local
814 if (SrcVT == MVT::i1 && Subtarget->useCRBits()) in PPCEmitCmp()
828 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || in PPCEmitCmp()
829 SrcVT == MVT::i8 || SrcVT == MVT::i1) { in PPCEmitCmp()
855 switch (SrcVT.SimpleTy) { in PPCEmitCmp()
920 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
926 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
945 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in SelectFPExt() local
948 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in SelectFPExt()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp181 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
182 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
185 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
187 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
188 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
190 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1003 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPExt() local
1006 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in selectFPExt()
1082 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPTrunc() local
1085 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in selectFPTrunc()
[all …]
H A DMipsMSAInstrInfo.td3536 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3538 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3539 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3593 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3596 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3597 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3601 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3604 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3605 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3609 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp194 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
228 Register emitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT, bool isZExt);
253 Register emitLSL_ri(MVT RetVT, MVT SrcVT, Register Op0Reg, uint64_t Imm,
256 Register emitLSR_ri(MVT RetVT, MVT SrcVT, Register Op0Reg, uint64_t Imm,
259 Register emitASR_ri(MVT RetVT, MVT SrcVT, Register Op0Reg, uint64_t Imm,
1183 MVT SrcVT = RetVT; in emitAddSub() local
1209 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1289 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
2833 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true); in selectFPToInt() local
2834 if (SrcVT == MVT::f128 || SrcVT == MVT::f16 || SrcVT == MVT::bf16) in selectFPToInt()
[all …]
H A DAArch64ISelLowering.cpp4356 EVT SrcVT = SrcVal.getValueType(); in LowerFP_ROUND() local
4361 if (SrcVT == MVT::nxv8f32) in LowerFP_ROUND()
4374 if (SrcVT == MVT::nxv2f32 || SrcVT == MVT::nxv4f32) { in LowerFP_ROUND()
4384 } else if (SrcVT == MVT::nxv2f64 && in LowerFP_ROUND()
4422 if (useSVEForFixedLengthVectorVT(SrcVT, !Subtarget->isNeonAvailable())) in LowerFP_ROUND()
4433 EVT I32 = SrcVT.changeElementType(MVT::i32); in LowerFP_ROUND()
4434 EVT F32 = SrcVT.changeElementType(MVT::f32); in LowerFP_ROUND()
4435 if (SrcVT.getScalarType() == MVT::f32) { in LowerFP_ROUND()
4443 } else if (SrcVT.getScalarType() == MVT::f64) { in LowerFP_ROUND()
4463 DL, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), SrcVT), in LowerFP_ROUND()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyTargetTransformInfo.cpp98 auto SrcVT = SrcTy.getSimpleVT(); in getCastInstrCost() local
108 if ((SrcVT == MVT::v8i8 && DstVT == MVT::v8i16) || in getCastInstrCost()
109 (SrcVT == MVT::v4i16 && DstVT == MVT::v4i32) || in getCastInstrCost()
110 (SrcVT == MVT::v2i32 && DstVT == MVT::v2i64)) { in getCastInstrCost()
115 if ((SrcVT == MVT::v4i8 && DstVT == MVT::v4i32) || in getCastInstrCost()
116 (SrcVT == MVT::v2i16 && DstVT == MVT::v2i64)) { in getCastInstrCost()
137 ConvertCostTableLookup(ConversionTbl, ISD, DstVT, SrcVT)) { in getCastInstrCost()
H A DWebAssemblyISelLowering.cpp2334 EVT SrcVT = Src.getValueType(); in LowerEXTEND_VECTOR_INREG() local
2336 if (SrcVT.getVectorElementType() == MVT::i1 || in LowerEXTEND_VECTOR_INREG()
2337 SrcVT.getVectorElementType() == MVT::i64) in LowerEXTEND_VECTOR_INREG()
2340 assert(VT.getScalarSizeInBits() % SrcVT.getScalarSizeInBits() == 0 && in LowerEXTEND_VECTOR_INREG()
2342 unsigned Scale = VT.getScalarSizeInBits() / SrcVT.getScalarSizeInBits(); in LowerEXTEND_VECTOR_INREG()
3137 EVT SrcVT = In.getValueType(); in truncateVectorWithNARROW() local
3140 if (SrcVT == DstVT) in truncateVectorWithNARROW()
3143 unsigned SrcSizeInBits = SrcVT.getSizeInBits(); in truncateVectorWithNARROW()
3144 unsigned NumElems = SrcVT.getVectorNumElements(); in truncateVectorWithNARROW()
3151 EVT PackedSVT = EVT::getIntegerVT(Ctx, SrcVT.getScalarSizeInBits() / 2); in truncateVectorWithNARROW()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp1407 EVT SrcVT = Src.getValueType(); in ExpandANY_EXTEND_VECTOR_INREG() local
1408 int NumSrcElements = SrcVT.getVectorNumElements(); in ExpandANY_EXTEND_VECTOR_INREG()
1412 if (SrcVT.bitsLE(VT)) { in ExpandANY_EXTEND_VECTOR_INREG()
1413 assert((VT.getSizeInBits() % SrcVT.getScalarSizeInBits()) == 0 && in ExpandANY_EXTEND_VECTOR_INREG()
1415 NumSrcElements = VT.getSizeInBits() / SrcVT.getScalarSizeInBits(); in ExpandANY_EXTEND_VECTOR_INREG()
1416 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getScalarType(), in ExpandANY_EXTEND_VECTOR_INREG()
1418 Src = DAG.getInsertSubvector(DL, DAG.getUNDEF(SrcVT), Src, 0); in ExpandANY_EXTEND_VECTOR_INREG()
1433 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask)); in ExpandANY_EXTEND_VECTOR_INREG()
1440 EVT SrcVT = Src.getValueType(); in ExpandSIGN_EXTEND_VECTOR_INREG() local
1450 unsigned SrcEltWidth = SrcVT.getScalarSizeInBits(); in ExpandSIGN_EXTEND_VECTOR_INREG()
[all …]
H A DTargetLowering.cpp724 EVT SrcVT = Src.getValueType(); in SimplifyMultipleUseDemandedBits() local
726 if (SrcVT == DstVT) in SimplifyMultipleUseDemandedBits()
729 unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits(); in SimplifyMultipleUseDemandedBits()
736 if (SrcVT.isVector() && (NumDstEltBits % NumSrcEltBits) == 0) { in SimplifyMultipleUseDemandedBits()
738 unsigned NumSrcElts = SrcVT.getVectorNumElements(); in SimplifyMultipleUseDemandedBits()
761 unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; in SimplifyMultipleUseDemandedBits()
910 EVT SrcVT = Src.getValueType(); in SimplifyMultipleUseDemandedBits() local
913 DstVT.getSizeInBits() == SrcVT.getSizeInBits() && in SimplifyMultipleUseDemandedBits()
914 DemandedBits.getActiveBits() <= SrcVT.getScalarSizeInBits()) { in SimplifyMultipleUseDemandedBits()
2493 EVT SrcVT = Src.getValueType(); in SimplifyDemandedBits() local
[all …]
H A DLegalizeDAG.cpp731 EVT SrcVT = LD->getMemoryVT(); in LegalizeLoadOps() local
732 TypeSize SrcWidth = SrcVT.getSizeInBits(); in LegalizeLoadOps()
736 if (SrcWidth != SrcVT.getStoreSizeInBits() && in LegalizeLoadOps()
744 (SrcVT != MVT::i1 || in LegalizeLoadOps()
749 unsigned NewWidth = SrcVT.getStoreSizeInBits(); in LegalizeLoadOps()
769 Result, DAG.getValueType(SrcVT)); in LegalizeLoadOps()
774 DAG.getValueType(SrcVT)); in LegalizeLoadOps()
780 assert(!SrcVT.isVector() && "Unsupported extload!"); in LegalizeLoadOps()
859 SrcVT.getSimpleVT())) { in LegalizeLoadOps()
887 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) { in LegalizeLoadOps()
[all …]
H A DFastISel.cpp1442 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); in selectCast() local
1445 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1455 if (!TLI.isTypeLegal(SrcVT)) in selectCast()
1463 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1480 MVT SrcVT = SrcEVT.getSimpleVT(); in selectBitCast() local
1487 if (SrcVT == DstVT) { in selectBitCast()
1493 Register ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0); in selectBitCast()
1852 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); in selectOperator() local
1854 if (DstVT.bitsGT(SrcVT)) in selectOperator()
1856 if (DstVT.bitsLT(SrcVT)) in selectOperator()
H A DDAGCombiner.cpp3851 static SDValue getTruncatedUSUBSAT(EVT DstVT, EVT SrcVT, SDValue LHS, in getTruncatedUSUBSAT() argument
3854 assert(DstVT.getScalarSizeInBits() <= SrcVT.getScalarSizeInBits() && in getTruncatedUSUBSAT()
3857 if (DstVT == SrcVT) in getTruncatedUSUBSAT()
3862 APInt UpperBits = APInt::getBitsSetFrom(SrcVT.getScalarSizeInBits(), in getTruncatedUSUBSAT()
3868 DAG.getConstant(APInt::getLowBitsSet(SrcVT.getScalarSizeInBits(), in getTruncatedUSUBSAT()
3870 DL, SrcVT); in getTruncatedUSUBSAT()
3871 RHS = DAG.getNode(ISD::UMIN, DL, SrcVT, RHS, SatLimit); in getTruncatedUSUBSAT()
7184 EVT SrcVT = Src.getValueType(); in combineShiftAnd1ToBitTest() local
7186 if (!TLI.isTypeLegal(SrcVT)) in combineShiftAnd1ToBitTest()
7190 unsigned BitWidth = SrcVT.getScalarSizeInBits(); in combineShiftAnd1ToBitTest()
[all …]
H A DLegalizeVectorTypes.cpp661 EVT SrcVT = Src.getValueType(); in ScalarizeVecRes_FP_TO_XINT_SAT() local
665 if (getTypeAction(SrcVT) == TargetLowering::TypeScalarizeVector) in ScalarizeVecRes_FP_TO_XINT_SAT()
669 ISD::EXTRACT_VECTOR_ELT, dl, SrcVT.getVectorElementType(), Src, in ScalarizeVecRes_FP_TO_XINT_SAT()
2697 EVT SrcVT = N->getOperand(0).getValueType(); in SplitVecRes_ExtendOp() local
2715 if (SrcVT.getVectorElementCount().isKnownEven() && in SplitVecRes_ExtendOp()
2716 SrcVT.getScalarSizeInBits() * 2 < DestVT.getScalarSizeInBits()) { in SplitVecRes_ExtendOp()
2718 EVT NewSrcVT = SrcVT.widenIntegerVectorElementType(Ctx); in SplitVecRes_ExtendOp()
2719 EVT SplitSrcVT = SrcVT.getHalfNumVectorElementsVT(Ctx); in SplitVecRes_ExtendOp()
2723 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) && in SplitVecRes_ExtendOp()
3142 EVT SrcVT = N->getOperand(0).getValueType(); in SplitVecRes_FP_TO_XINT_SAT() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp225 Register ARMEmitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT, bool isZExt);
1386 MVT SrcVT = SrcEVT.getSimpleVT(); in ARMEmitCmp() local
1402 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || in ARMEmitCmp()
1403 SrcVT == MVT::i1) { in ARMEmitCmp()
1417 if (SrcVT == MVT::f32 || SrcVT == MVT::f64) in ARMEmitCmp()
1425 switch (SrcVT.SimpleTy) { in ARMEmitCmp()
1469 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); in ARMEmitCmp()
1473 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1587 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP() local
1588 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in SelectIToFP()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp86 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, Register Src, EVT SrcVT,
701 EVT SrcVT, Register &ResultReg) { in X86FastEmitExtend() argument
702 Register RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); in X86FastEmitExtend()
1244 EVT SrcVT = TLI.getValueType(DL, RV->getType()); in X86SelectRet() local
1247 if (SrcVT != DstVT) { in X86SelectRet()
1248 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) in X86SelectRet()
1254 if (SrcVT == MVT::i1) { in X86SelectRet()
1258 SrcVT = MVT::i8; in X86SelectRet()
1260 if (SrcVT != DstVT) { in X86SelectRet()
1264 fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg); in X86SelectRet()
[all …]
H A DX86ISelLowering.cpp3371 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
3379 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) && in isExtractSubvectorCheap()
5258 EVT SrcVT = Op.getOperand(0).getValueType(); in getTargetConstantBitsFromNode() local
5259 unsigned NumSrcElts = SrcVT.getSizeInBits() / EltSizeInBits; in getTargetConstantBitsFromNode()
5263 assert((SrcVT.getSizeInBits() % EltSizeInBits) == 0 && in getTargetConstantBitsFromNode()
6372 EVT SrcVT = SrcVec.getValueType(); in getFauxShuffleMask() local
6373 if (!SrcVT.getScalarType().isByteSized()) in getFauxShuffleMask()
6376 unsigned SrcByte = SrcIdx * (SrcVT.getScalarSizeInBits() / 8); in getFauxShuffleMask()
6379 std::min<unsigned>(MinBitsPerElt, SrcVT.getScalarSizeInBits()); in getFauxShuffleMask()
6470 EVT SrcVT = Src.getValueType(); in getFauxShuffleMask() local
[all …]
H A DX86SelectionDAGInfo.cpp311 EVT SrcVT = Src.getValueType(); in emitConstantSizeRepmov() local
315 DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, dl, SrcVT)), in emitConstantSizeRepmov()
H A DX86ISelLowering.h1470 bool isNarrowingProfitable(SDNode *N, EVT SrcVT, EVT DestVT) const override;
1536 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
1605 std::pair<SDValue, SDValue> BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL,
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTypePromotion.cpp939 EVT SrcVT = TLI->getValueType(DL, I->getType()); in run() local
940 if (SrcVT.isSimple() && TLI->isTypeLegal(SrcVT.getSimpleVT())) in run()
943 if (TLI->getTypeAction(*Ctx, SrcVT) != TargetLowering::TypePromoteInteger) in run()
946 EVT PromotedVT = TLI->getTypeToTransformTo(*Ctx, SrcVT); in run()
947 if (TLI->isSExtCheaperThanZExt(SrcVT, PromotedVT)) in run()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1038 bool AMDGPUTargetLowering::isNarrowingProfitable(SDNode *N, EVT SrcVT, in isNarrowingProfitable() argument
1062 SrcVT.getScalarSizeInBits() > 16) { in isNarrowingProfitable()
1078 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32; in isNarrowingProfitable()
1605 EVT SrcVT = Op.getOperand(0).getValueType(); in LowerEXTRACT_SUBVECTOR() local
1609 unsigned NumSrcElt = SrcVT.getVectorNumElements(); in LowerEXTRACT_SUBVECTOR()
3414 EVT SrcVT = Src.getValueType(); in LowerUINT_TO_FP() local
3416 if (SrcVT == MVT::i16) { in LowerUINT_TO_FP()
3433 if (SrcVT != MVT::i64) in LowerUINT_TO_FP()
3460 EVT SrcVT = Src.getValueType(); in LowerSINT_TO_FP() local
3462 if (SrcVT == MVT::i16) { in LowerSINT_TO_FP()
[all …]
H A DSIInstrInfo.td327 class isIntType<ValueType SrcVT> {
328 bit ret = !and(SrcVT.isInteger, !ne(SrcVT.Value, i1.Value));
1914 class isModifierType<ValueType SrcVT> {
1915 bit ret = !or(!eq(SrcVT.Value, f16.Value),
1916 !eq(SrcVT.Value, bf16.Value),
1917 !eq(SrcVT.Value, f32.Value),
1918 !eq(SrcVT.Value, f64.Value),
1919 !eq(SrcVT.Value, v2f16.Value),
1920 !eq(SrcVT.Value, v2i16.Value),
1921 !eq(SrcVT.Value, v2bf16.Value),
[all …]
H A DSIISelLowering.h304 EVT SrcVT) const override;
375 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h47 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
50 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
67 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
618 bool shouldMergeStoreOfLoadsOverCall(EVT SrcVT, EVT MergedVT) const override { in shouldMergeStoreOfLoadsOverCall() argument
619 return !MergedVT.isVector() || SrcVT.isVector(); in shouldMergeStoreOfLoadsOverCall()
H A DRISCVISelLowering.cpp2072 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { in isTruncateFree() argument
2075 if (SrcVT.isVector() || DstVT.isVector() || !SrcVT.isInteger() || in isTruncateFree()
2078 unsigned SrcBits = SrcVT.getSizeInBits(); in isTruncateFree()
2084 EVT SrcVT = Val.getValueType(); in isTruncateFree() local
2088 SrcVT.isVector() && VT2.isVector()) { in isTruncateFree()
2089 unsigned SrcBits = SrcVT.getVectorElementType().getSizeInBits(); in isTruncateFree()
2113 bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const { in isSExtCheaperThanZExt() argument
2114 return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64; in isSExtCheaperThanZExt()
2340 bool RISCVTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
2350 if (ResVT.isScalableVector() || SrcVT.isScalableVector()) in isExtractSubvectorCheap()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2718 static unsigned decideComp(EVT SrcVT, ISD::CondCode CC) { in decideComp() argument
2719 if (SrcVT.isFloatingPoint()) { in decideComp()
2720 if (SrcVT == MVT::f128) in decideComp()
2727 static EVT decideCompType(EVT SrcVT) { in decideCompType() argument
2728 if (SrcVT == MVT::f128) in decideCompType()
2730 return SrcVT; in decideCompType()
2733 static bool safeWithoutCompWithNull(EVT SrcVT, ISD::CondCode CC, in safeWithoutCompWithNull() argument
2735 if (SrcVT.isFloatingPoint()) { in safeWithoutCompWithNull()
2740 return SrcVT != MVT::f128; in safeWithoutCompWithNull()
2755 return isSignedIntSetCC(CC) && SrcVT == MVT::i64; in safeWithoutCompWithNull()

123