1019 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {  in isNarrowingProfitable()  argument
1026   return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;  in isNarrowingProfitable()
1548   EVT SrcVT = Op.getOperand(0).getValueType();  in LowerEXTRACT_SUBVECTOR()  local
1552     unsigned NumSrcElt = SrcVT.getVectorNumElements();  in LowerEXTRACT_SUBVECTOR()
3356   EVT SrcVT = Src.getValueType();  in LowerUINT_TO_FP()  local
3358   if (SrcVT == MVT::i16) {  in LowerUINT_TO_FP()
3375   if (SrcVT != MVT::i64)  in LowerUINT_TO_FP()
3402   EVT SrcVT = Src.getValueType();  in LowerSINT_TO_FP()  local
3404   if (SrcVT == MVT::i16) {  in LowerSINT_TO_FP()
3421   if (SrcVT != MVT::i64)  in LowerSINT_TO_FP()
3451   EVT SrcVT = Src.getValueType();  in LowerFP_TO_INT64()  local
3453   assert(SrcVT == MVT::f32 || SrcVT == MVT::f64);  in LowerFP_TO_INT64()
3464   SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, SrcVT, Src);  in LowerFP_TO_INT64()
3466   if (Signed && SrcVT == MVT::f32) {  in LowerFP_TO_INT64()
3475     Trunc = DAG.getNode(ISD::FABS, SL, SrcVT, Trunc);  in LowerFP_TO_INT64()
3479   if (SrcVT == MVT::f64) {  in LowerFP_TO_INT64()
3482         SrcVT);  in LowerFP_TO_INT64()
3485         SrcVT);  in LowerFP_TO_INT64()
3488         llvm::bit_cast<float>(UINT32_C(/*2^-32*/ 0x2f800000)), SL, SrcVT);  in LowerFP_TO_INT64()
3490         llvm::bit_cast<float>(UINT32_C(/*-2^32*/ 0xcf800000)), SL, SrcVT);  in LowerFP_TO_INT64()
3493   SDValue Mul = DAG.getNode(ISD::FMUL, SL, SrcVT, Trunc, K0);  in LowerFP_TO_INT64()
3495   SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, SrcVT, Mul);  in LowerFP_TO_INT64()
3497   SDValue Fma = DAG.getNode(ISD::FMA, SL, SrcVT, FloorMul, K1, Trunc);  in LowerFP_TO_INT64()
3499   SDValue Hi = DAG.getNode((Signed && SrcVT == MVT::f64) ? ISD::FP_TO_SINT  in LowerFP_TO_INT64()
3507   if (Signed && SrcVT == MVT::f32) {  in LowerFP_TO_INT64()
3624   EVT SrcVT = Src.getValueType();  in LowerFP_TO_INT()  local
3628   if (SrcVT == MVT::f16 && DestVT == MVT::i16)  in LowerFP_TO_INT()
3631   if (SrcVT == MVT::bf16) {  in LowerFP_TO_INT()
3638   if (DestVT == MVT::i16 && (SrcVT == MVT::f32 || SrcVT == MVT::f64)) {  in LowerFP_TO_INT()
3648   if (SrcVT == MVT::f16 ||  in LowerFP_TO_INT()
3649       (SrcVT == MVT::f32 && Src.getOpcode() == ISD::FP16_TO_FP)) {  in LowerFP_TO_INT()
3658   if (SrcVT == MVT::f32 || SrcVT == MVT::f64)  in LowerFP_TO_INT()
3920     EVT SrcVT = Src.getValueType();  in performAssertSZExtCombine()  local
3921     if (SrcVT.bitsGE(ExtVT)) {  in performAssertSZExtCombine()
3922       SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1);  in performAssertSZExtCombine()
4191     EVT SrcVT = Src.getValueType();  in performTruncateCombine()  local
4192     if (SrcVT.getScalarSizeInBits() > 32 &&  in performTruncateCombine()
4934     EVT SrcVT = Src.getValueType();  in performFNegCombine()  local
4937     SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src,  in performFNegCombine()
4938                                   DAG.getConstant(0x8000, SL, SrcVT));  in performFNegCombine()
5020     EVT SrcVT = Src.getValueType();  in performFAbsCombine()  local
5023     SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src,  in performFAbsCombine()
5024                                   DAG.getConstant(0x7fff, SL, SrcVT));  in performFAbsCombine()
5065         EVT SrcVT = Src.getValueType();  in PerformDAGCombine()  local
5068         if (SrcVT.getVectorNumElements() == NElts) {  in PerformDAGCombine()
5073           for (unsigned I = 0, E = SrcVT.getVectorNumElements(); I != E; ++I) {  in PerformDAGCombine()