| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMCCodeEmitter.cpp | 249 MCRegister SrcReg1 = MI.getOperand(0).getReg(); in expandLongCondBr() local
259 if (RISCV::X8 <= SrcReg1.id() && SrcReg1.id() <= RISCV::X15 && in expandLongCondBr()
263 SrcReg1.id() == RISCV::X0) { in expandLongCondBr()
264 std::swap(SrcReg1, SrcReg2); in expandLongCondBr()
273 MCInst TmpInst = MCInstBuilder(InvOpc).addReg(SrcReg1).addImm(6); in expandLongCondBr()
280 MCInstBuilder(InvOpc).addReg(SrcReg1).addReg(SrcReg2).addImm(8); in expandLongCondBr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 850 Register SrcReg1 = getRegForValue(SrcValue1); in PPCEmitCmp() local
851 if (SrcReg1 == 0) in PPCEmitCmp()
864 auto RC1 = MRI.getRegClass(SrcReg1); in PPCEmitCmp()
886 SrcReg1 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg1); in PPCEmitCmp()
932 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
934 SrcReg1 = ExtReg; in PPCEmitCmp()
946 .addReg(SrcReg1).addReg(SrcReg2); in PPCEmitCmp()
949 .addReg(SrcReg1).addImm(Imm); in PPCEmitCmp()
1300 Register SrcReg1 = getRegForValue(I->getOperand(0)); in SelectBinaryIntOp() local
1301 if (SrcReg1 == 0) return false; in SelectBinaryIntOp()
[all …]
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| H A D | PPCInstrInfo.cpp | 5404 Register SrcReg1 = MI->getOperand(1).getReg(); in isSignOrZeroExtended() local
5406 auto Src1Ext = isSignOrZeroExtended(SrcReg1, BinOpDepth + 1, MRI); in isSignOrZeroExtended()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PreLegalizerCombiner.cpp | 562 Register DstReg, Register SrcReg1, Register SrcReg2) { in matchPushAddSubExt() argument
574 LLT Ext1SrcTy = MRI.getType(SrcReg1); in matchPushAddSubExt()
588 Register SrcReg1, Register SrcReg2) { in applyPushAddSubExt() argument
589 LLT SrcTy = MRI.getType(SrcReg1); in applyPushAddSubExt()
592 Register Ext1Reg = B.buildInstr(Opc, {MidTy}, {SrcReg1}).getReg(0); in applyPushAddSubExt()
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| H A D | AArch64LegalizerInfo.cpp | 1409 Register SrcReg1 = MI.getOperand(2).getReg(); in legalizeICMP() local
1412 LLT SrcTy = MRI.getType(SrcReg1); in legalizeICMP()
1427 .buildICmp(CmpInst::ICMP_EQ, MRI.getType(DstReg), SrcReg1, SrcReg2) in legalizeICMP()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SIMDInstrOpt.cpp | 436 Register SrcReg1 = MI.getOperand(2).getReg(); in optimizeVectElement()
456 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
460 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg1, LaneNumber, &DupDest)) { in optimizeVectElement()
463 .addReg(SrcReg1, Src1IsKill) in optimizeVectElement()
435 Register SrcReg1 = MI.getOperand(2).getReg(); optimizeVectElement() local
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| H A D | AArch64InstrInfo.cpp | 4813 Register SrcReg1 = SrcReg; in storeRegPairToStackSlot() local
4817 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1); in storeRegPairToStackSlot()
4822 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
6670 Register SrcReg1 = MUL->getOperand(2).getReg(); in genFusedMultiply() local
6688 if (SrcReg1.isVirtual()) in genFusedMultiply()
6689 MRI.constrainRegClass(SrcReg1, RC); in genFusedMultiply()
6697 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply()
6703 .addReg(SrcReg1, getKillRegState(Src1IsKill)) in genFusedMultiply()
6709 .addReg(SrcReg1, getKillRegState(Src1IsKill)); in genFusedMultiply()
6734 Register SrcReg1 = MAD->getOperand(2).getReg(); in genFNegatedMAD() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1412 Register SrcReg1 = getRegForValue(Src1Value); in ARMEmitCmp() local
1413 if (SrcReg1 == 0) return false; in ARMEmitCmp()
1423 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); in ARMEmitCmp()
1424 if (SrcReg1 == 0) return false; in ARMEmitCmp()
1432 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0); in ARMEmitCmp()
1436 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1440 .addReg(SrcReg1); in ARMEmitCmp()
1758 Register SrcReg1 = getRegForValue(I->getOperand(0)); in SelectBinaryIntOp() local
1759 if (SrcReg1 == 0) return false; in SelectBinaryIntOp()
1767 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1); in SelectBinaryIntOp()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 2557 Register SrcReg1 = MI.getOperand(2).getReg(); in applyMappingImpl() local
2571 MRI.setRegClass(SrcReg1, &AMDGPU::SGPR_64RegClass); in applyMappingImpl()
2592 B.buildTrunc(Op1L, SrcReg1); in applyMappingImpl()
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