Lines Matching refs:SrcReg1
1412 Register SrcReg1 = getRegForValue(Src1Value); in ARMEmitCmp() local
1413 if (SrcReg1 == 0) return false; in ARMEmitCmp()
1423 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); in ARMEmitCmp()
1424 if (SrcReg1 == 0) return false; in ARMEmitCmp()
1432 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0); in ARMEmitCmp()
1436 .addReg(SrcReg1).addReg(SrcReg2)); in ARMEmitCmp()
1440 .addReg(SrcReg1); in ARMEmitCmp()
1758 Register SrcReg1 = getRegForValue(I->getOperand(0)); in SelectBinaryIntOp() local
1759 if (SrcReg1 == 0) return false; in SelectBinaryIntOp()
1767 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1); in SelectBinaryIntOp()
1771 .addReg(SrcReg1).addReg(SrcReg2)); in SelectBinaryIntOp()