Searched refs:SrcReg0 (Results 1 – 5 of 5) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SIMDInstrOpt.cpp | 434 Register SrcReg0 = MI.getOperand(1).getReg(); in optimizeVectElement()
455 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
467 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
433 Register SrcReg0 = MI.getOperand(1).getReg(); optimizeVectElement() local
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| H A D | AArch64InstrInfo.cpp | 4812 Register SrcReg0 = SrcReg; in storeRegPairToStackSlot() local
4815 SrcReg0 = TRI.getSubReg(SrcReg, SubIdx0); in storeRegPairToStackSlot()
4821 .addReg(SrcReg0, getKillRegState(IsKill), SubIdx0) in storeRegPairToStackSlot()
6668 Register SrcReg0 = MUL->getOperand(1).getReg(); in genFusedMultiply() local
6686 if (SrcReg0.isVirtual()) in genFusedMultiply()
6687 MRI.constrainRegClass(SrcReg0, RC); in genFusedMultiply()
6696 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
6702 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
6708 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
6733 Register SrcReg0 = MAD->getOperand(1).getReg(); in genFNegatedMAD() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 1447 Register SrcReg0 = I.getOperand(1).getReg(); in selectMergeValues() local
1450 const LLT SrcTy = MRI.getType(SrcReg0); in selectMergeValues()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 2556 Register SrcReg0 = MI.getOperand(1).getReg(); in applyMappingImpl() local
2570 MRI.setRegClass(SrcReg0, &AMDGPU::SGPR_64RegClass); in applyMappingImpl()
2586 B.buildTrunc(Op0L, SrcReg0); in applyMappingImpl()
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