Lines Matching refs:SrcReg0
4812 Register SrcReg0 = SrcReg; in storeRegPairToStackSlot() local
4815 SrcReg0 = TRI.getSubReg(SrcReg, SubIdx0); in storeRegPairToStackSlot()
4821 .addReg(SrcReg0, getKillRegState(IsKill), SubIdx0) in storeRegPairToStackSlot()
6668 Register SrcReg0 = MUL->getOperand(1).getReg(); in genFusedMultiply() local
6686 if (SrcReg0.isVirtual()) in genFusedMultiply()
6687 MRI.constrainRegClass(SrcReg0, RC); in genFusedMultiply()
6696 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
6702 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
6708 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
6733 Register SrcReg0 = MAD->getOperand(1).getReg(); in genFNegatedMAD() local
6741 if (SrcReg0.isVirtual()) in genFNegatedMAD()
6742 MRI.constrainRegClass(SrcReg0, RC); in genFNegatedMAD()
6750 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFNegatedMAD()
6899 Register SrcReg0 = MUL->getOperand(1).getReg(); in genMaddR() local
6906 if (SrcReg0.isVirtual()) in genMaddR()
6907 MRI.constrainRegClass(SrcReg0, RC); in genMaddR()
6915 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genMaddR()