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Searched refs:SrcRC (Results 1 – 25 of 50) sorted by relevance

12

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp195 const TargetRegisterClass *SrcRC = SrcReg.isVirtual() in getCopyRegClasses() local
206 return std::pair(SrcRC, DstRC); in getCopyRegClasses()
209 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, in isVGPRToSGPRCopy() argument
212 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && in isVGPRToSGPRCopy()
213 TRI.hasVectorRegisters(SrcRC); in isVGPRToSGPRCopy()
216 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, in isSGPRToVGPRCopy() argument
219 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) && in isSGPRToVGPRCopy()
285 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
286 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
288 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence()
[all …]
H A DAMDGPUInstructionSelector.cpp114 const TargetRegisterClass *SrcRC in constrainCopyLikeIntrin() local
116 if (!DstRC || DstRC != SrcRC) in constrainCopyLikeIntrin()
120 RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI); in constrainCopyLikeIntrin()
147 const TargetRegisterClass *SrcRC in selectCOPY() local
158 Register MaskedReg = MRI->createVirtualRegister(SrcRC); in selectCOPY()
164 bool IsSGPR = TRI.isSGPRClass(SrcRC); in selectCOPY()
179 MRI->setRegClass(SrcReg, SrcRC); in selectCOPY()
518 const TargetRegisterClass *SrcRC = in selectG_EXTRACT() local
520 if (!SrcRC) in selectG_EXTRACT()
524 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubReg); in selectG_EXTRACT()
[all …]
H A DSIRegisterInfo.h272 const TargetRegisterClass *SrcRC,
316 const TargetRegisterClass *SrcRC,
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in copyPhysReg() local
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
49 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr in copyPhysReg()
52 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr in copyPhysReg()
57 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr in copyPhysReg()
60 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr in copyPhysReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp
H A DX86DomainReassignment.cpp66 static const TargetRegisterClass *getDstRC(const TargetRegisterClass *SrcRC, in getDstRC() argument
69 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
71 if (X86::GR16RegClass.hasSubClassEq(SrcRC)) in getDstRC()
73 if (X86::GR32RegClass.hasSubClassEq(SrcRC)) in getDstRC()
75 if (X86::GR64RegClass.hasSubClassEq(SrcRC)) in getDstRC()
H A DX86InstrMMX.td123 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
126 def rr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
127 [(set DstRC:$dst, (Int SrcRC:$src))], d>,
134 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
138 (ins DstRC:$src1, SrcRC:$src2), asm,
139 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>,
H A DX86RegisterInfo.h78 const TargetRegisterClass *SrcRC,
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp114 const TargetRegisterClass *SrcRC) const;
293 const TargetRegisterClass *SrcRC = in selectCopy() local
297 if (SrcRC != DstRC) { in selectCopy()
305 .addImm(getSubRegIndex(SrcRC)); in selectCopy()
331 const TargetRegisterClass *SrcRC = getRegClassFromGRPhysReg(SrcReg); in selectCopy() local
333 if (DstRC != SrcRC) { in selectCopy()
768 const TargetRegisterClass *SrcRC) { in canTurnIntoCOPY() argument
771 (SrcRC == &X86::VR128RegClass || SrcRC == &X86::VR128XRegClass); in canTurnIntoCOPY()
777 const TargetRegisterClass *SrcRC) const { in selectTurnIntoCOPY()
779 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in selectTurnIntoCOPY()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp382 const TargetRegisterClass *SrcRC, in shareSameRegisterFile() argument
385 if (DefRC == SrcRC) in shareSameRegisterFile()
391 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
399 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
404 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
407 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
412 const TargetRegisterClass *SrcRC, in shouldRewriteCopySrc() argument
415 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
H A DDetectDeadLanes.cpp73 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy() local
74 if (DstRC == SrcRC) in isCrossCopy()
99 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
102 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
104 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
105 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
H A DMachineCombiner.cpp176 auto SrcRC = MRI->getRegClass(Src); in isTransientMI() local
178 return TRI->getMatchingSuperRegClass(SrcRC, DstRC, SrcSub) != nullptr; in isTransientMI()
185 auto SrcRC = MRI->getRegClass(Src); in isTransientMI() local
187 return SrcRC->hasSuperClassEq(DstRC) || SrcRC->hasSubClassEq(DstRC); in isTransientMI()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp133 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in foldSimpleCrossClassCopies() local
136 if (SrcRC == DstRC) in foldSimpleCrossClassCopies()
140 if (SrcRC->hasSubClass(DstRC)) { in foldSimpleCrossClassCopies()
152 } else if (DstRC->hasSubClass(SrcRC)) { in foldSimpleCrossClassCopies()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp99 const TargetRegisterClass *SrcRC = &PPC::VSLRCRegClass; in processBlock() local
105 Register NewVReg = MRI.createVirtualRegister(SrcRC); in processBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMips32r6InstrInfo.td660 RegisterOperand SrcRC, InstrItinClass Itin> {
661 dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
670 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
673 dag InOperandList = (ins SrcRC:$rt);
676 list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
682 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
684 dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
696 RegisterOperand SrcRC, InstrItinClass Itin> {
697 dag InOperandList = (ins SrcRC:$rt);
718 RegisterOperand SrcRC, InstrItinClass Itin> {
[all …]
H A DMipsInstrFPU.td128 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
130 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
131 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
135 class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
138 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft),
140 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
162 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
164 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
165 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT {
169 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp878 const TargetRegisterClass *SrcRC, in shouldCoalesce() argument
893 getRegSizeInBits(*SrcRC) < 256) in shouldCoalesce()
899 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC); in shouldCoalesce()
938 const TargetRegisterClass *SrcRC, in shouldRewriteCopySrc() argument
942 SrcRC == &ARM::DPRRegClass && in shouldRewriteCopySrc()
947 SrcRC, SrcSubReg); in shouldRewriteCopySrc()
H A DARMBaseRegisterInfo.h230 const TargetRegisterClass *SrcRC,
239 const TargetRegisterClass *SrcRC,
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.h54 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
H A DAVRRegisterInfo.cpp314 MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, in shouldCoalesce() argument
321 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, in shouldCoalesce()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.h59 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp240 auto SrcRC = MRI.getRegClass(SrcReg); in runOnMachineFunction() local
242 if (SrcRC == DstRC) { in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp380 const TargetRegisterClass *SrcRC, in shouldCoalesce() argument
390 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64) && in shouldCoalesce()
397 unsigned SubregOpIdx = getRegSizeInBits(*SrcRC) == 128 ? 0 : 1; in shouldCoalesce()
H A DSystemZRegisterInfo.h171 const TargetRegisterClass *SrcRC,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h141 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,

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