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Searched refs:SrcOp (Results 1 – 25 of 49) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h131 class SrcOp {
141 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {} in SrcOp() function
142 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {} in SrcOp() function
143 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {} in SrcOp() function
144 SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {} in SrcOp() function
148 SrcOp(unsigned) = delete;
149 SrcOp(int) = delete;
150 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} in SrcOp() function
151 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} in SrcOp() function
228 unsigned getOpcodeForMerge(const DstOp &DstOp, ArrayRef<SrcOp> SrcOps) const;
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H A DCSEMIRBuilder.h63 void profileSrcOp(const SrcOp &Op, GISelInstProfileBuilder &B) const;
65 void profileSrcOps(ArrayRef<SrcOp> Ops, GISelInstProfileBuilder &B) const { in profileSrcOps()
66 for (const SrcOp &Op : Ops) in profileSrcOps()
73 ArrayRef<SrcOp> SrcOps, std::optional<unsigned> Flags,
95 buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps,
H A DLegalizationArtifactCombiner.h1124 unsigned SrcOp = SrcDef->getOpcode(); in tryCombineUnmergeValues() local
1125 if (isArtifactCast(SrcOp)) { in tryCombineUnmergeValues()
1126 ConvertOp = SrcOp; in tryCombineUnmergeValues()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp137 const SrcOp &Size, in buildDynStackAlloc()
202 MachineIRBuilder::buildPtrAdd(const DstOp &Res, const SrcOp &Op0, in buildPtrAdd()
203 const SrcOp &Op1, std::optional<unsigned> Flags) { in buildPtrAdd()
228 const SrcOp &Op0, in buildMaskLowPtrBits()
239 const SrcOp &Op0) { in buildPadVectorWithUndefElements()
270 const SrcOp &Op0) { in buildDeleteTrailingVectorElements()
313 const SrcOp &Op) { in buildCopy()
413 MachineInstrBuilder MachineIRBuilder::buildBrCond(const SrcOp &Tst, in buildBrCond()
424 MachineIRBuilder::buildLoad(const DstOp &Dst, const SrcOp &Addr, in buildLoad()
439 const SrcOp &Addr, in buildLoadInstr()
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H A DCSEMIRBuilder.cpp90 void CSEMIRBuilder::profileSrcOp(const SrcOp &Op, in profileSrcOp()
93 case SrcOp::SrcType::Ty_Imm: in profileSrcOp()
96 case SrcOp::SrcType::Ty_Predicate: in profileSrcOp()
114 ArrayRef<SrcOp> SrcOps, in profileEverything()
177 ArrayRef<SrcOp> SrcOps, in buildInstr()
261 const SrcOp &Src0 = SrcOps[0]; in buildInstr()
262 const SrcOp &Src1 = SrcOps[1]; in buildInstr()
/freebsd/contrib/llvm-project/llvm/lib/Linker/
H A DIRMover.cpp1293 MDNode *SrcOp = SrcModFlags->getOperand(I); in linkModuleFlagsMetadata() local
1295 mdconst::extract<ConstantInt>(SrcOp->getOperand(0)); in linkModuleFlagsMetadata()
1296 MDString *ID = cast<MDString>(SrcOp->getOperand(1)); in linkModuleFlagsMetadata()
1307 if (Requirements.insert(cast<MDNode>(SrcOp->getOperand(2)))) { in linkModuleFlagsMetadata()
1308 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1319 Flags[ID] = std::make_pair(SrcOp, DstModFlags->getNumOperands()); in linkModuleFlagsMetadata()
1320 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1330 DstModFlags->setOperand(DstIndex, SrcOp); in linkModuleFlagsMetadata()
1331 Flags[ID].first = SrcOp; in linkModuleFlagsMetadata()
1338 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVInstrInfo.cpp251 auto SrcOp = I->getOperand(1); in copyPhysReg() local
252 assert(DstOp.isReg() && SrcOp.isReg() && in copyPhysReg()
255 MRI.replaceRegWith(DstOp.getReg(), SrcOp.getReg()); in copyPhysReg()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenInstruction.cpp357 std::pair<unsigned, unsigned> SrcOp = (FirstIsDest ? RHSOp : LHSOp); in ParseConstraint() local
365 if (SrcOp.first < Ops.NumDefs) in ParseConstraint()
373 if (!Ops[SrcOp.first].Constraints[SrcOp.second].isNone()) in ParseConstraint()
391 Ops[SrcOp.first].Constraints[SrcOp.second] = NewConstraint; in ParseConstraint()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp217 MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
644 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, in genCondTfrFor() argument
648 MachineInstr *MI = SrcOp.getParent(); in genCondTfrFor()
658 unsigned Opc = getCondTfrOpcode(SrcOp, PredSense); in genCondTfrFor()
663 if (SrcOp.isReg()) { in genCondTfrFor()
664 unsigned SrcState = getRegState(SrcOp); in genCondTfrFor()
665 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR)) in genCondTfrFor()
670 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg()); in genCondTfrFor()
675 .add(SrcOp); in genCondTfrFor()
H A DHexagonRDFOpt.cpp144 const MachineOperand &SrcOp = MI->getOperand(1); in INITIALIZE_PASS_DEPENDENCY() local
146 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonFrameLowering.cpp2408 MachineOperand &SrcOp = SI.getOperand(2); in optimizeSpillSlots() local
2410 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(), in optimizeSpillSlots()
2411 SrcOp.getSubReg() }; in optimizeSpillSlots()
2433 .add(SrcOp); in optimizeSpillSlots()
2440 if (unsigned SR = SrcOp.getSubReg()) in optimizeSpillSlots()
2441 SrcOp.setReg(HRI.getSubReg(FoundR, SR)); in optimizeSpillSlots()
2443 SrcOp.setReg(FoundR); in optimizeSpillSlots()
2444 SrcOp.setSubReg(0); in optimizeSpillSlots()
2446 SrcOp.setIsKill(false); in optimizeSpillSlots()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILowerControlFlow.cpp586 for (const auto &SrcOp : Def->explicit_operands()) in findMaskOperands() local
587 if (SrcOp.isReg() && SrcOp.isUse() && in findMaskOperands()
588 (SrcOp.getReg().isVirtual() || SrcOp.getReg() == Exec)) in findMaskOperands()
589 Src.push_back(SrcOp); in findMaskOperands()
H A DSIPeepholeSDWA.cpp143 const MachineOperand *SrcOp) const;
313 const MachineOperand *SrcOp) const { in getSrcMods()
315 const auto *MI = SrcOp->getParent(); in getSrcMods()
316 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
320 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) { in getSrcMods()
H A DSIInstrInfo.cpp2189 const MachineOperand &SrcOp = MI.getOperand(1); in expandPostRAPseudo() local
2191 assert(!SrcOp.isFPImm()); in expandPostRAPseudo()
2194 if (SrcOp.isReg() || isInlineConstant(MI, 1) || in expandPostRAPseudo()
2195 isUInt<32>(SrcOp.getImm())) in expandPostRAPseudo()
2198 if (SrcOp.isImm()) { in expandPostRAPseudo()
2199 APInt Imm(64, SrcOp.getImm()); in expandPostRAPseudo()
2222 assert(SrcOp.isReg()); in expandPostRAPseudo()
2224 !RI.isAGPR(MBB.getParent()->getRegInfo(), SrcOp.getReg())) { in expandPostRAPseudo()
2227 .addReg(SrcOp.getReg()) in expandPostRAPseudo()
2229 .addReg(SrcOp.getReg()) in expandPostRAPseudo()
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H A DSIFoldOperands.cpp877 const auto &SrcOp = UseMI->getOperand(UseOpIdx); in foldOperand() local
878 MachineOperand NewSrcOp(SrcOp); in foldOperand()
1491 auto &SrcOp = InstToErase->getOperand(1); in tryFoldFoldableCopy() local
1492 auto SrcReg = SrcOp.isReg() ? SrcOp.getReg() : Register(); in tryFoldFoldableCopy()
H A DAMDGPULegalizerInfo.cpp6225 MachineOperand &SrcOp = MI.getOperand(ArgOffset + I); in packImage16bitOpsToDwords() local
6226 if (!SrcOp.isReg()) in packImage16bitOpsToDwords()
6229 Register AddrReg = SrcOp.getReg(); in packImage16bitOpsToDwords()
6282 MachineOperand &SrcOp = MI.getOperand(DimIdx + I); in convertImageAddrToPacked() local
6283 if (SrcOp.isReg()) { in convertImageAddrToPacked()
6284 AddrRegs.push_back(SrcOp.getReg()); in convertImageAddrToPacked()
6285 assert(B.getMRI()->getType(SrcOp.getReg()) == S32); in convertImageAddrToPacked()
6297 MachineOperand &SrcOp = MI.getOperand(DimIdx + I); in convertImageAddrToPacked() local
6298 if (SrcOp.isReg()) in convertImageAddrToPacked()
6464 MachineOperand &SrcOp = MI.getOperand(ArgOffset + I); in legalizeImageIntrinsic() local
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DInlineSpiller.cpp261 const MachineOperand &SrcOp = MI.getOperand(1); in isCopyOf() local
264 if (DstOp.getSubReg() != SrcOp.getSubReg()) in isCopyOf()
267 return SrcOp.getReg(); in isCopyOf()
268 if (SrcOp.getReg() == Reg) in isCopyOf()
291 const MachineOperand &SrcOp = *CopyInst->Source; in isCopyOfBundle() local
294 SnipReg = SrcOp.getReg(); in isCopyOfBundle()
295 else if (SnipReg != SrcOp.getReg()) in isCopyOfBundle()
297 } else if (SrcOp.getReg() == Reg) { in isCopyOfBundle()
H A DMachineVerifier.cpp1578 const MachineOperand &SrcOp = MI->getOperand(1); in verifyPreISelGenericInstruction() local
1579 if (!SrcOp.isReg()) { in verifyPreISelGenericInstruction()
1591 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits(); in verifyPreISelGenericInstruction()
1600 const MachineOperand &SrcOp = MI->getOperand(2); in verifyPreISelGenericInstruction() local
1601 if (!SrcOp.isReg()) { in verifyPreISelGenericInstruction()
1613 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits(); in verifyPreISelGenericInstruction()
1751 const MachineOperand &SrcOp = MI->getOperand(1); in verifyPreISelGenericInstruction() local
1752 if (!SrcOp.isReg()) { in verifyPreISelGenericInstruction()
1764 LLT SrcTy = MRI->getType(SrcOp.getReg()); in verifyPreISelGenericInstruction()
2228 const MachineOperand &SrcOp = MI->getOperand(1); in visitMachineInstrBefore() local
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineNegator.cpp253 Value *SrcOp = I->getOperand(0); in visitImpl() local
254 unsigned SrcWidth = SrcOp->getType()->getScalarSizeInBits(); in visitImpl()
257 match(SrcOp, m_LShr(m_Value(X), m_SpecificIntAllowPoison(FullShift)))) { in visitImpl()
H A DInstCombineCasts.cpp1172 if (auto *SrcOp = dyn_cast<Instruction>(Src)) in visitZExt() local
1173 if (SrcOp->hasOneUse()) in visitZExt()
1174 replaceAllDbgUsesWith(*SrcOp, *Res, Zext, DT); in visitZExt()
2032 Value *SrcOp = CI.getPointerOperand(); in visitPtrToInt() local
2033 Type *SrcTy = SrcOp->getType(); in visitPtrToInt()
2041 Value *P = Builder.CreatePtrToInt(SrcOp, IntPtrTy); in visitPtrToInt()
2049 if (match(SrcOp, m_OneUse(m_Intrinsic<Intrinsic::ptrmask>(m_Value(Ptr), in visitPtrToInt()
2054 if (auto *GEP = dyn_cast<GEPOperator>(SrcOp)) { in visitPtrToInt()
2082 if (match(SrcOp, m_OneUse(m_InsertElt(m_IntToPtr(m_Value(Vec)), in visitPtrToInt()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMIRYamlMapping.h519 unsigned SrcOp;
525 return std::tie(SrcInst, SrcOp, DstInst, DstOp) ==
526 std::tie(Other.SrcInst, Other.SrcOp, Other.DstInst, Other.DstOp);
533 YamlIO.mapRequired("srcop", Sub.SrcOp);
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SelectionDAGInfo.cpp78 auto *SrcOp = in EmitMOPS() local
80 DAG.setNodeMemRefs(Node, {DstOp, SrcOp}); in EmitMOPS()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp665 static MachineInstrBuilder buildAllOnesMask(LLT VecTy, const SrcOp &VL, in buildAllOnesMask()
685 buildSplatPartsS64WithVL(const DstOp &Dst, const SrcOp &Passthru, Register Lo, in buildSplatPartsS64WithVL()
701 buildSplatSplitS64WithVL(const DstOp &Dst, const SrcOp &Passthru, in buildSplatSplitS64WithVL()
702 const SrcOp &Scalar, Register VL, in buildSplatSplitS64WithVL()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DInstructionSimplify.cpp3809 Value *SrcOp = LI->getOperand(0); in simplifyICmpInst() local
3810 Type *SrcTy = SrcOp->getType(); in simplifyICmpInst()
3819 if (Value *V = simplifyICmpInst(Pred, SrcOp, in simplifyICmpInst()
3826 if (Value *V = simplifyICmpInst(Pred, SrcOp, RI->getOperand(0), Q, in simplifyICmpInst()
3839 simplifyICmpInst(ICmpInst::getUnsignedPredicate(Pred), SrcOp, in simplifyICmpInst()
3845 if (SrcOp == RI->getOperand(0)) { in simplifyICmpInst()
3875 SrcOp, Trunc, Q, MaxRecurse - 1)) in simplifyICmpInst()
3918 if (Value *V = simplifyICmpInst(Pred, SrcOp, RI->getOperand(0), Q, in simplifyICmpInst()
3924 if (SrcOp == RI->getOperand(0)) { in simplifyICmpInst()
3952 simplifyICmpInst(Pred, SrcOp, Trunc, Q, MaxRecurse - 1)) in simplifyICmpInst()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp75 SmallVector<SrcOp, 2> SrcOps; ///< Source registers.
77 std::initializer_list<SrcOp> SrcOps) in ShuffleVectorPseudo()

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