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Searched refs:SrcOp (Results 1 – 25 of 51) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h143 class SrcOp {
153 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {} in SrcOp() function
154 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {} in SrcOp() function
155 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {} in SrcOp() function
156 SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {} in SrcOp() function
160 SrcOp(unsigned) = delete;
161 SrcOp(int) = delete;
162 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} in SrcOp() function
163 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} in SrcOp() function
240 unsigned getOpcodeForMerge(const DstOp &DstOp, ArrayRef<SrcOp> SrcOps) const;
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H A DCSEMIRBuilder.h70 void profileSrcOp(const SrcOp &Op, GISelInstProfileBuilder &B) const;
72 void profileSrcOps(ArrayRef<SrcOp> Ops, GISelInstProfileBuilder &B) const { in profileSrcOps()
73 for (const SrcOp &Op : Ops) in profileSrcOps()
80 ArrayRef<SrcOp> SrcOps, std::optional<unsigned> Flags,
102 buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps,
H A DLegalizationArtifactCombiner.h1137 unsigned SrcOp = SrcDef->getOpcode(); in tryCombineUnmergeValues() local
1138 if (isArtifactCast(SrcOp)) { in tryCombineUnmergeValues()
1139 ConvertOp = SrcOp; in tryCombineUnmergeValues()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp137 const SrcOp &Size, in buildDynStackAlloc()
202 MachineIRBuilder::buildPtrAdd(const DstOp &Res, const SrcOp &Op0, in buildPtrAdd()
203 const SrcOp &Op1, std::optional<unsigned> Flags) { in buildPtrAdd()
228 const SrcOp &Op0, in buildMaskLowPtrBits()
239 const SrcOp &Op0) { in buildPadVectorWithUndefElements()
270 const SrcOp &Op0) { in buildDeleteTrailingVectorElements()
313 const SrcOp &Op) { in buildCopy()
415 MachineInstrBuilder MachineIRBuilder::buildBrCond(const SrcOp &Tst, in buildBrCond()
426 MachineIRBuilder::buildLoad(const DstOp &Dst, const SrcOp &Addr, in buildLoad()
441 const SrcOp &Addr, in buildLoadInstr()
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H A DCSEMIRBuilder.cpp94 void CSEMIRBuilder::profileSrcOp(const SrcOp &Op, in profileSrcOp()
97 case SrcOp::SrcType::Ty_Imm: in profileSrcOp()
100 case SrcOp::SrcType::Ty_Predicate: in profileSrcOp()
118 ArrayRef<SrcOp> SrcOps, in profileEverything()
181 ArrayRef<SrcOp> SrcOps, in buildInstr()
267 const SrcOp &Src0 = SrcOps[0]; in buildInstr()
268 const SrcOp &Src1 = SrcOps[1]; in buildInstr()
/freebsd/contrib/llvm-project/llvm/lib/Linker/
H A DIRMover.cpp1185 MDNode *SrcOp = SrcModFlags->getOperand(I); in linkModuleFlagsMetadata() local
1187 mdconst::extract<ConstantInt>(SrcOp->getOperand(0)); in linkModuleFlagsMetadata()
1188 MDString *ID = cast<MDString>(SrcOp->getOperand(1)); in linkModuleFlagsMetadata()
1199 if (Requirements.insert(cast<MDNode>(SrcOp->getOperand(2)))) { in linkModuleFlagsMetadata()
1200 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1211 Flags[ID] = std::make_pair(SrcOp, DstModFlags->getNumOperands()); in linkModuleFlagsMetadata()
1212 DstModFlags->addOperand(SrcOp); in linkModuleFlagsMetadata()
1222 DstModFlags->setOperand(DstIndex, SrcOp); in linkModuleFlagsMetadata()
1223 Flags[ID].first = SrcOp; in linkModuleFlagsMetadata()
1230 SrcOp->getOperand(2) != DstOp->getOperand(2)) in linkModuleFlagsMetadata()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVInstrInfo.cpp282 auto SrcOp = I->getOperand(1); in copyPhysReg() local
283 assert(DstOp.isReg() && SrcOp.isReg() && in copyPhysReg()
286 MRI.replaceRegWith(DstOp.getReg(), SrcOp.getReg()); in copyPhysReg()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenInstruction.cpp353 std::pair<unsigned, unsigned> SrcOp = (FirstIsDest ? RHSOp : LHSOp); in ParseConstraint() local
361 if (SrcOp.first < Ops.NumDefs) in ParseConstraint()
369 if (!Ops[SrcOp.first].Constraints[SrcOp.second].isNone()) in ParseConstraint()
387 Ops[SrcOp.first].Constraints[SrcOp.second] = NewConstraint; in ParseConstraint()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp210 MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
627 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, in genCondTfrFor() argument
631 MachineInstr *MI = SrcOp.getParent(); in genCondTfrFor()
641 unsigned Opc = getCondTfrOpcode(SrcOp, PredSense); in genCondTfrFor()
646 if (SrcOp.isReg()) { in genCondTfrFor()
647 unsigned SrcState = getRegState(SrcOp); in genCondTfrFor()
648 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR)) in genCondTfrFor()
653 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg()); in genCondTfrFor()
658 .add(SrcOp); in genCondTfrFor()
H A DHexagonRDFOpt.cpp137 const MachineOperand &SrcOp = MI->getOperand(1); in INITIALIZE_PASS_DEPENDENCY() local
139 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonFrameLowering.cpp2394 MachineOperand &SrcOp = SI.getOperand(2); in optimizeSpillSlots() local
2396 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(), in optimizeSpillSlots()
2397 SrcOp.getSubReg() }; in optimizeSpillSlots()
2419 .add(SrcOp); in optimizeSpillSlots()
2426 if (unsigned SR = SrcOp.getSubReg()) in optimizeSpillSlots()
2427 SrcOp.setReg(HRI.getSubReg(FoundR, SR)); in optimizeSpillSlots()
2429 SrcOp.setReg(FoundR); in optimizeSpillSlots()
2430 SrcOp.setSubReg(0); in optimizeSpillSlots()
2432 SrcOp.setIsKill(false); in optimizeSpillSlots()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp905 MachineOperand &SrcOp = SubDef->getOperand(1); in lookUpCopyChain() local
906 if (SrcOp.isImm()) in lookUpCopyChain()
907 return &SrcOp; in lookUpCopyChain()
908 if (!SrcOp.isReg() || SrcOp.getReg().isPhysical()) in lookUpCopyChain()
910 Sub = &SrcOp; in lookUpCopyChain()
912 if (SrcOp.getSubReg()) in lookUpCopyChain()
928 MachineOperand &SrcOp = RegSeq.getOperand(I); in getRegSeqInit() local
932 const TargetRegisterClass *OpRC = getRegOpRC(*MRI, *TRI, SrcOp); in getRegSeqInit()
938 if (SrcOp.getSubReg()) { in getRegSeqInit()
940 Defs.emplace_back(&SrcOp, SubRegIdx); in getRegSeqInit()
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H A DSILowerControlFlow.cpp595 for (const auto &SrcOp : Def->explicit_operands()) in findMaskOperands() local
596 if (SrcOp.isReg() && SrcOp.isUse() && in findMaskOperands()
597 (SrcOp.getReg().isVirtual() || SrcOp.getReg() == Exec)) in findMaskOperands()
598 Src.push_back(SrcOp); in findMaskOperands()
H A DSIPeepholeSDWA.cpp157 const MachineOperand *SrcOp) const;
362 const MachineOperand *SrcOp) const { in getSrcMods()
364 const auto *MI = SrcOp->getParent(); in getSrcMods()
365 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
369 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) { in getSrcMods()
H A DSIInstrInfo.cpp2211 const MachineOperand &SrcOp = MI.getOperand(1); in expandPostRAPseudo() local
2213 assert(!SrcOp.isFPImm()); in expandPostRAPseudo()
2216 if (SrcOp.isReg() || isInlineConstant(MI, 1) || in expandPostRAPseudo()
2217 isUInt<32>(SrcOp.getImm()) || ST.has64BitLiterals()) in expandPostRAPseudo()
2220 if (SrcOp.isImm()) { in expandPostRAPseudo()
2221 APInt Imm(64, SrcOp.getImm()); in expandPostRAPseudo()
2244 assert(SrcOp.isReg()); in expandPostRAPseudo()
2246 !RI.isAGPR(MBB.getParent()->getRegInfo(), SrcOp.getReg())) { in expandPostRAPseudo()
2249 .addReg(SrcOp.getReg()) in expandPostRAPseudo()
2251 .addReg(SrcOp.getReg()) in expandPostRAPseudo()
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H A DAMDGPULegalizerInfo.cpp6355 MachineOperand &SrcOp = MI.getOperand(ArgOffset + I); in packImage16bitOpsToDwords() local
6356 if (!SrcOp.isReg()) in packImage16bitOpsToDwords()
6359 Register AddrReg = SrcOp.getReg(); in packImage16bitOpsToDwords()
6412 MachineOperand &SrcOp = MI.getOperand(DimIdx + I); in convertImageAddrToPacked() local
6413 if (SrcOp.isReg()) { in convertImageAddrToPacked()
6414 AddrRegs.push_back(SrcOp.getReg()); in convertImageAddrToPacked()
6415 assert(B.getMRI()->getType(SrcOp.getReg()) == S32); in convertImageAddrToPacked()
6427 MachineOperand &SrcOp = MI.getOperand(DimIdx + I); in convertImageAddrToPacked() local
6428 if (SrcOp.isReg()) in convertImageAddrToPacked()
6594 MachineOperand &SrcOp = MI.getOperand(ArgOffset + I); in legalizeImageIntrinsic() local
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DPseudoLoweringEmitter.cpp176 for (const auto &[Idx, SrcOp] : enumerate(SourceInsn.Operands)) in evaluateExpansion()
177 SourceOperands[SrcOp.Name] = Idx; in evaluateExpansion()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DInlineSpiller.cpp260 const MachineOperand &SrcOp = MI.getOperand(1); in isCopyOf() local
263 if (DstOp.getSubReg() != SrcOp.getSubReg()) in isCopyOf()
266 return SrcOp.getReg(); in isCopyOf()
267 if (SrcOp.getReg() == Reg) in isCopyOf()
290 const MachineOperand &SrcOp = *CopyInst->Source; in isCopyOfBundle() local
293 SnipReg = SrcOp.getReg(); in isCopyOfBundle()
294 else if (SnipReg != SrcOp.getReg()) in isCopyOfBundle()
296 } else if (SrcOp.getReg() == Reg) { in isCopyOfBundle()
H A DMachineVerifier.cpp1640 const MachineOperand &SrcOp = MI->getOperand(1); in verifyPreISelGenericInstruction() local
1641 if (!SrcOp.isReg()) { in verifyPreISelGenericInstruction()
1653 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits(); in verifyPreISelGenericInstruction()
1662 const MachineOperand &SrcOp = MI->getOperand(2); in verifyPreISelGenericInstruction() local
1663 if (!SrcOp.isReg()) { in verifyPreISelGenericInstruction()
1675 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits(); in verifyPreISelGenericInstruction()
1853 const MachineOperand &SrcOp = MI->getOperand(1); in verifyPreISelGenericInstruction() local
1854 if (!SrcOp.isReg()) { in verifyPreISelGenericInstruction()
1866 LLT SrcTy = MRI->getType(SrcOp.getReg()); in verifyPreISelGenericInstruction()
2358 const MachineOperand &SrcOp = MI->getOperand(1); in visitMachineInstrBefore() local
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineNegator.cpp249 Value *SrcOp = I->getOperand(0); in visitImpl() local
250 unsigned SrcWidth = SrcOp->getType()->getScalarSizeInBits(); in visitImpl()
253 match(SrcOp, m_LShr(m_Value(X), m_SpecificIntAllowPoison(FullShift)))) { in visitImpl()
H A DInstCombineCasts.cpp1226 if (auto *SrcOp = dyn_cast<Instruction>(Src)) in visitZExt() local
1227 if (SrcOp->hasOneUse()) in visitZExt()
1228 replaceAllDbgUsesWith(*SrcOp, *Res, Zext, DT); in visitZExt()
2118 Value *SrcOp = CI.getPointerOperand(); in visitPtrToInt() local
2119 Type *SrcTy = SrcOp->getType(); in visitPtrToInt()
2127 Value *P = Builder.CreatePtrToInt(SrcOp, IntPtrTy); in visitPtrToInt()
2135 if (match(SrcOp, m_OneUse(m_Intrinsic<Intrinsic::ptrmask>(m_Value(Ptr), in visitPtrToInt()
2140 if (Value *V = foldPtrToIntOfGEP(Ty, SrcOp)) in visitPtrToInt()
2144 if (match(SrcOp, m_OneUse(m_InsertElt(m_IntToPtr(m_Value(Vec)), in visitPtrToInt()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMIRYamlMapping.h522 unsigned SrcOp;
528 return std::tie(SrcInst, SrcOp, DstInst, DstOp) ==
529 std::tie(Other.SrcInst, Other.SrcOp, Other.DstInst, Other.DstOp);
536 YamlIO.mapRequired("srcop", Sub.SrcOp);
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SelectionDAGInfo.cpp153 auto *SrcOp = in EmitMOPS() local
155 DAG.setNodeMemRefs(Node, {DstOp, SrcOp}); in EmitMOPS()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp960 static MachineInstrBuilder buildAllOnesMask(LLT VecTy, const SrcOp &VL, in buildAllOnesMask()
980 buildSplatPartsS64WithVL(const DstOp &Dst, const SrcOp &Passthru, Register Lo, in buildSplatPartsS64WithVL()
981 Register Hi, const SrcOp &VL, MachineIRBuilder &MIB, in buildSplatPartsS64WithVL()
996 buildSplatSplitS64WithVL(const DstOp &Dst, const SrcOp &Passthru, in buildSplatSplitS64WithVL()
997 const SrcOp &Scalar, const SrcOp &VL, in buildSplatSplitS64WithVL()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLatencyMutations.cpp84 bool isMVEIntMACMatched(unsigned SrcOp, unsigned DstOp) { in isMVEIntMACMatched() argument
85 return SrcOp == DstOp || Info[DstOp].MVEIntMACMatched == SrcOp; in isMVEIntMACMatched()

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