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Searched refs:SrcMI (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp236 MachineInstr *SrcMI = MRI->getUniqueVRegDef(MI.getOperand(2).getReg()); in visitORR() local
237 if (!SrcMI) in visitORR()
250 if (SrcMI->getOpcode() == TargetOpcode::COPY && in visitORR()
251 SrcMI->getOperand(1).getReg().isVirtual()) { in visitORR()
253 MRI->getRegClass(SrcMI->getOperand(1).getReg()); in visitORR()
259 SrcMI->getOperand(1).getSubReg() != AArch64::ssub)) in visitORR()
261 Register CpySrc = SrcMI->getOperand(1).getReg(); in visitORR()
262 if (SrcMI->getOperand(1).getSubReg() == AArch64::ssub) { in visitORR()
264 BuildMI(*SrcMI->getParent(), SrcMI, SrcMI->getDebugLoc(), in visitORR()
266 .add(SrcMI->getOperand(1)); in visitORR()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DOptimizePHIs.cpp115 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle() local
118 if (SrcMI && SrcMI->isCopy() && !SrcMI->getOperand(0).getSubReg() && in IsSingleValuePHICycle()
119 !SrcMI->getOperand(1).getSubReg() && in IsSingleValuePHICycle()
120 SrcMI->getOperand(1).getReg().isVirtual()) { in IsSingleValuePHICycle()
121 SrcReg = SrcMI->getOperand(1).getReg(); in IsSingleValuePHICycle()
122 SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle()
124 if (!SrcMI) in IsSingleValuePHICycle()
127 if (SrcMI->isPHI()) { in IsSingleValuePHICycle()
128 if (!IsSingleValuePHICycle(SrcMI, SingleValReg, PHIsInCycle)) in IsSingleValuePHICycle()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp941 MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg); in simplifyCode() local
942 unsigned SrcOpcode = SrcMI->getOpcode(); in simplifyCode()
946 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg())) in simplifyCode()
972 LLVM_DEBUG(SrcMI->dump()); in simplifyCode()
976 SrcMI->setDesc(TII->get(Opc)); in simplifyCode()
977 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
992 MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg); in simplifyCode() local
993 unsigned SrcOpcode = SrcMI->getOpcode(); in simplifyCode()
997 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg())) in simplifyCode()
1005 if (SrcMI->getOperand(1).isGlobal()) { in simplifyCode()
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H A DPPCInstrInfo.cpp2796 MachineInstr *SrcMI = getDefMIPostRA(SrcReg, CmpMI, SrcRegHasOtherUse); in optimizeCmpPostRA() local
2797 if (!SrcMI || !SrcMI->definesRegister(SrcReg, /*TRI=*/nullptr)) in optimizeCmpPostRA()
2808 if (!isRegElgibleForForwarding(RegMO, *SrcMI, CmpMI, false, IsCRRegKilled, in optimizeCmpPostRA()
2810 SrcMI->definesRegister(CRReg, /*TRI=*/nullptr) || SeenUseOfCRReg) in optimizeCmpPostRA()
2813 int SrcMIOpc = SrcMI->getOpcode(); in optimizeCmpPostRA()
2819 LLVM_DEBUG(SrcMI->dump()); in optimizeCmpPostRA()
2822 SrcMI->setDesc(NewDesc); in optimizeCmpPostRA()
2823 MachineInstrBuilder(*SrcMI->getParent()->getParent(), SrcMI) in optimizeCmpPostRA()
2825 SrcMI->clearRegisterDeads(CRReg); in optimizeCmpPostRA()
2827 assert(SrcMI->definesRegister(PPC::CR0, /*TRI=*/nullptr) && in optimizeCmpPostRA()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp206 MachineInstr *SrcMI = MRI.getUniqueVRegDef(Src); in foldCopyDup() local
207 if (!SrcMI || SrcMI->getOpcode() != DUP || !MRI.hasOneNonDBGUse(Src)) in foldCopyDup()
210 Register DupSrc = SrcMI->getOperand(1).getReg(); in foldCopyDup()
211 int64_t DupImm = SrcMI->getOperand(2).getImm(); in foldCopyDup()
216 SrcMI->eraseFromParent(); in foldCopyDup()
H A DAArch64InstructionSelector.cpp4585 MachineInstr *SrcMI = MRI->getVRegDef(CarryReg); in emitCarryIn() local
4586 if (SrcMI == I.getPrevNode()) { in emitCarryIn()
4587 if (auto *CarrySrcMI = dyn_cast<GAddSubCarryOut>(SrcMI)) { in emitCarryIn()
4592 selectAndRestoreState(*SrcMI)) in emitCarryIn()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h98 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineAnyExt() local
99 if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) { in tryCombineAnyExt()
102 auto &CstVal = SrcMI->getOperand(1); in tryCombineAnyExt()
104 MI.getDebugLoc().get(), SrcMI->getDebugLoc().get()); in tryCombineAnyExt()
111 markInstAndDefDead(MI, *SrcMI, DeadInsts); in tryCombineAnyExt()
178 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineZExt() local
179 if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) { in tryCombineZExt()
182 auto &CstVal = SrcMI->getOperand(1); in tryCombineZExt()
186 markInstAndDefDead(MI, *SrcMI, DeadInsts); in tryCombineZExt()
242 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineSExt() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp87 MachineInstr *SrcMI = MRI.getVRegDef(SrcReg); in addConstantsToTrack() local
88 if (SrcMI && (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT || in addConstantsToTrack()
89 SrcMI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)) in addConstantsToTrack()
90 TargetExtConstTypes[SrcMI] = Const->getType(); in addConstantsToTrack()
95 SrcMI->setDesc(STI.getInstrInfo()->get(SPIRV::OpConstantNull)); in addConstantsToTrack()
96 SrcMI->addOperand(MachineOperand::CreateReg( in addConstantsToTrack()
105 MachineInstr *SrcMI = MRI.getVRegDef(MI.getOperand(2).getReg()); in addConstantsToTrack() local
106 if (SrcMI && isSpvIntrinsic(*SrcMI, Intrinsic::spv_const_composite)) in addConstantsToTrack()
107 ToEraseComposites.push_back(SrcMI); in addConstantsToTrack()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ControlFlowFinalizer.cpp266 unsigned DstMI, SrcMI; in isCompatibleWithClause() local
285 SrcMI = Reg; in isCompatibleWithClause()
287 SrcMI = TRI->getMatchingSuperReg(Reg, in isCompatibleWithClause()
292 if ((DstRegs.find(SrcMI) == DstRegs.end())) { in isCompatibleWithClause()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp2541 MachineInstr *SrcMI = MRI.getVRegDef(SrcReg); in matchCombineExtOfExt() local
2544 unsigned SrcOpc = SrcMI->getOpcode(); in matchCombineExtOfExt()
2549 MatchInfo = std::make_tuple(SrcMI->getOperand(1).getReg(), SrcOpc); in matchCombineExtOfExt()
2589 MachineInstr *SrcMI = MRI.getVRegDef(SrcReg); in matchCombineTruncOfExt() local
2590 unsigned SrcOpc = SrcMI->getOpcode(); in matchCombineTruncOfExt()
2593 MatchInfo = std::make_pair(SrcMI->getOperand(1).getReg(), SrcOpc); in matchCombineTruncOfExt()
2648 MachineInstr *SrcMI = getDefIgnoringCopies(SrcReg, MRI); in matchCombineTruncOfShift() local
2652 switch (SrcMI->getOpcode()) { in matchCombineTruncOfShift()
2659 KnownBits Known = KB->getKnownBits(SrcMI->getOperand(2).getReg()); in matchCombineTruncOfShift()
2680 KnownBits Known = KB->getKnownBits(SrcMI->getOperand(2).getReg()); in matchCombineTruncOfShift()
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