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Searched refs:SrcMI (Results 1 – 14 of 14) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp242 MachineInstr *SrcMI = MRI->getUniqueVRegDef(MI.getOperand(2).getReg()); in visitORR() local
243 if (!SrcMI) in visitORR()
256 if (SrcMI->getOpcode() == TargetOpcode::COPY && in visitORR()
257 SrcMI->getOperand(1).getReg().isVirtual()) { in visitORR()
259 MRI->getRegClass(SrcMI->getOperand(1).getReg()); in visitORR()
266 SrcMI->getOperand(1).getSubReg() != AArch64::ssub)) in visitORR()
269 if (SrcMI->getOperand(1).getSubReg() == AArch64::ssub) { in visitORR()
271 BuildMI(*SrcMI->getParent(), SrcMI, SrcMI->getDebugLoc(), in visitORR()
273 .add(SrcMI->getOperand(1)); in visitORR()
275 CpySrc = SrcMI->getOperand(1).getReg(); in visitORR()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DOptimizePHIs.cpp130 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle() local
133 if (SrcMI && SrcMI->isCopy() && !SrcMI->getOperand(0).getSubReg() && in IsSingleValuePHICycle()
134 !SrcMI->getOperand(1).getSubReg() && in IsSingleValuePHICycle()
135 SrcMI->getOperand(1).getReg().isVirtual()) { in IsSingleValuePHICycle()
136 SrcReg = SrcMI->getOperand(1).getReg(); in IsSingleValuePHICycle()
137 SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle()
139 if (!SrcMI) in IsSingleValuePHICycle()
142 if (SrcMI->isPHI()) { in IsSingleValuePHICycle()
143 if (!IsSingleValuePHICycle(SrcMI, SingleValReg, PHIsInCycle)) in IsSingleValuePHICycle()
H A DMachinePipeliner.cpp1007 MachineInstr &SrcMI = *Src.SU->getInstr(); in hasLoopCarriedMemDep() local
1018 if (TII->getMemOperandWithOffset(SrcMI, BaseOp1, Offset1, Offset1IsScalable, in hasLoopCarriedMemDep()
1025 assert(TII->areMemAccessesTriviallyDisjoint(SrcMI, DstMI) && in hasLoopCarriedMemDep()
1032 if (!SSD->mayOverlapInLaterIter(&SrcMI, &DstMI)) in hasLoopCarriedMemDep()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLatencyMutations.cpp532 const MachineInstr *SrcMI = ISU.getInstr(); in makeBundleAssumptions() local
533 unsigned SrcOpcode = SrcMI->getOpcode(); in makeBundleAssumptions()
543 if (SrcOpcode == ARM::BUNDLE && TII->isPredicated(*SrcMI) && in makeBundleAssumptions()
608 const MachineInstr *SrcMI = ISU.getInstr(); in modifyBypasses() local
609 unsigned SrcOpcode = SrcMI->getOpcode(); in modifyBypasses()
667 if (TII->isPredicated(*SrcMI) && Dep.isAssignedRegDep() && in modifyBypasses()
669 mismatchedPred(TII->getPredicate(*SrcMI), in modifyBypasses()
720 signed modifyMixedWidthFP(const MachineInstr *SrcMI,
749 signed M85Overrides::modifyMixedWidthFP(const MachineInstr *SrcMI, in modifyMixedWidthFP() argument
754 if (!II->producesSP(SrcMI->getOpcode()) && in modifyMixedWidthFP()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp936 MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg); in simplifyCode() local
937 unsigned SrcOpcode = SrcMI->getOpcode(); in simplifyCode()
941 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg())) in simplifyCode()
967 LLVM_DEBUG(SrcMI->dump()); in simplifyCode()
971 SrcMI->setDesc(TII->get(Opc)); in simplifyCode()
972 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
987 MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg); in simplifyCode() local
988 unsigned SrcOpcode = SrcMI->getOpcode(); in simplifyCode()
992 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg())) in simplifyCode()
1000 if (SrcMI->getOperand(1).isGlobal()) { in simplifyCode()
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H A DPPCInstrInfo.cpp2819 MachineInstr *SrcMI = getDefMIPostRA(SrcReg, CmpMI, SrcRegHasOtherUse); in optimizeCmpPostRA() local
2820 if (!SrcMI || !SrcMI->definesRegister(SrcReg, /*TRI=*/nullptr)) in optimizeCmpPostRA()
2831 if (!isRegElgibleForForwarding(RegMO, *SrcMI, CmpMI, false, IsCRRegKilled, in optimizeCmpPostRA()
2833 SrcMI->definesRegister(CRReg, /*TRI=*/nullptr) || SeenUseOfCRReg) in optimizeCmpPostRA()
2836 int SrcMIOpc = SrcMI->getOpcode(); in optimizeCmpPostRA()
2842 LLVM_DEBUG(SrcMI->dump()); in optimizeCmpPostRA()
2845 SrcMI->setDesc(NewDesc); in optimizeCmpPostRA()
2846 MachineInstrBuilder(*SrcMI->getParent()->getParent(), SrcMI) in optimizeCmpPostRA()
2848 SrcMI->clearRegisterDeads(CRReg); in optimizeCmpPostRA()
2850 assert(SrcMI->definesRegister(PPC::CR0, /*TRI=*/nullptr) && in optimizeCmpPostRA()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVVMV0Elimination.cpp130 if (MachineInstr *SrcMI = MRI.getVRegDef(Src); in runOnMachineFunction() local
131 SrcMI->isCopy() && SrcMI->getOperand(1).getReg().isVirtual() && in runOnMachineFunction()
132 SrcMI->getOperand(1).getSubReg() == RISCV::NoSubRegister) { in runOnMachineFunction()
135 DeadCopies.push_back(SrcMI); in runOnMachineFunction()
136 Src = SrcMI->getOperand(1).getReg(); in runOnMachineFunction()
H A DRISCVOptWInstrs.cpp608 if (MachineInstr *SrcMI = MRI.getVRegDef(MI->getOperand(1).getReg())) { in isSignExtendedW() local
609 if (SrcMI->getOpcode() == RISCV::LUI && in isSignExtendedW()
610 SrcMI->getOperand(1).isImm()) { in isSignExtendedW()
611 uint64_t Imm = SrcMI->getOperand(1).getImm(); in isSignExtendedW()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp201 MachineInstr *SrcMI = MRI.getUniqueVRegDef(Src); in foldCopyDup() local
202 if (!SrcMI || SrcMI->getOpcode() != DUP || !MRI.hasOneNonDBGUse(Src)) in foldCopyDup()
205 Register DupSrc = SrcMI->getOperand(1).getReg(); in foldCopyDup()
206 int64_t DupImm = SrcMI->getOperand(2).getImm(); in foldCopyDup()
211 SrcMI->eraseFromParent(); in foldCopyDup()
H A DAArch64InstructionSelector.cpp4720 MachineInstr *SrcMI = MRI->getVRegDef(CarryReg); in emitCarryIn() local
4721 if (SrcMI == I.getPrevNode()) { in emitCarryIn()
4722 if (auto *CarrySrcMI = dyn_cast<GAddSubCarryOut>(SrcMI)) { in emitCarryIn()
4727 selectAndRestoreState(*SrcMI)) in emitCarryIn()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h98 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineAnyExt() local
99 if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) { in tryCombineAnyExt()
102 auto &CstVal = SrcMI->getOperand(1); in tryCombineAnyExt()
104 DebugLoc::getMergedLocation(MI.getDebugLoc(), SrcMI->getDebugLoc()); in tryCombineAnyExt()
111 markInstAndDefDead(MI, *SrcMI, DeadInsts); in tryCombineAnyExt()
178 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineZExt() local
179 if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) { in tryCombineZExt()
182 auto &CstVal = SrcMI->getOperand(1); in tryCombineZExt()
186 markInstAndDefDead(MI, *SrcMI, DeadInsts); in tryCombineZExt()
242 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineSExt() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp90 MachineInstr *SrcMI = MRI.getVRegDef(SrcReg); in addConstantsToTrack() local
91 if (SrcMI) in addConstantsToTrack()
92 GR->add(Const, SrcMI); in addConstantsToTrack()
93 if (SrcMI && (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT || in addConstantsToTrack()
94 SrcMI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)) in addConstantsToTrack()
95 TargetExtConstTypes[SrcMI] = Const->getType(); in addConstantsToTrack()
102 SrcMI->setDesc(STI.getInstrInfo()->get(SPIRV::OpConstantNull)); in addConstantsToTrack()
103 SrcMI->addOperand(MachineOperand::CreateReg( in addConstantsToTrack()
112 MachineInstr *SrcMI = MRI.getVRegDef(MI.getOperand(2).getReg()); in addConstantsToTrack() local
113 if (SrcMI && isSpvIntrinsic(*SrcMI, Intrinsic::spv_const_composite)) in addConstantsToTrack()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ControlFlowFinalizer.cpp266 unsigned DstMI, SrcMI; in isCompatibleWithClause() local
285 SrcMI = Reg; in isCompatibleWithClause()
287 SrcMI = TRI->getMatchingSuperReg(Reg, in isCompatibleWithClause()
292 if ((DstRegs.find(SrcMI) == DstRegs.end())) { in isCompatibleWithClause()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp2668 MachineInstr *SrcMI = getDefIgnoringCopies(SrcReg, MRI); in matchCombineTruncOfShift() local
2672 switch (SrcMI->getOpcode()) { in matchCombineTruncOfShift()
2679 KnownBits Known = VT->getKnownBits(SrcMI->getOperand(2).getReg()); in matchCombineTruncOfShift()
2700 KnownBits Known = VT->getKnownBits(SrcMI->getOperand(2).getReg()); in matchCombineTruncOfShift()
2709 {SrcMI->getOpcode(), in matchCombineTruncOfShift()
2713 MatchInfo = std::make_pair(SrcMI, NewShiftTy); in matchCombineTruncOfShift()
3459 auto SrcMI = MRI.getVRegDef(BuildMI->getSourceReg(I)); in matchUseVectorTruncate() local
3460 auto SrcMIOpc = SrcMI->getOpcode(); in matchUseVectorTruncate()
3465 UnmergeMI = MRI.getVRegDef(SrcMI->getOperand(1).getReg()); in matchUseVectorTruncate()
3469 auto UnmergeSrcMI = MRI.getVRegDef(SrcMI->getOperand(1).getReg()); in matchUseVectorTruncate()
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