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Searched refs:Src1SubRC (Results 1 – 2 of 2) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp7858 const TargetRegisterClass *Src1SubRC = in splitScalarSMulU64() local
7860 if (RI.isSGPRClass(Src1SubRC)) in splitScalarSMulU64()
7861 Src1SubRC = RI.getEquivalentVGPRClass(Src1SubRC); in splitScalarSMulU64()
7868 buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in splitScalarSMulU64()
7872 buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in splitScalarSMulU64()
7967 const TargetRegisterClass *Src1SubRC = in splitScalarSMulPseudo() local
7969 if (RI.isSGPRClass(Src1SubRC)) in splitScalarSMulPseudo()
7970 Src1SubRC = RI.getEquivalentVGPRClass(Src1SubRC); in splitScalarSMulPseudo()
7977 buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in splitScalarSMulPseudo()
8032 const TargetRegisterClass *Src1SubRC = in splitScalar64BitBinaryOp() local
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H A DSIISelLowering.cpp5081 const TargetRegisterClass *Src1SubRC = in EmitInstrWithCustomInserter() local
5087 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in EmitInstrWithCustomInserter()
5092 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in EmitInstrWithCustomInserter()
5308 const TargetRegisterClass *Src1SubRC = in EmitInstrWithCustomInserter() local
5314 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in EmitInstrWithCustomInserter()
5319 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in EmitInstrWithCustomInserter()