7858   const TargetRegisterClass *Src1SubRC =  in splitScalarSMulU64()  local
7860   if (RI.isSGPRClass(Src1SubRC))  in splitScalarSMulU64()
7861     Src1SubRC = RI.getEquivalentVGPRClass(Src1SubRC);  in splitScalarSMulU64()
7868       buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);  in splitScalarSMulU64()
7872       buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC);  in splitScalarSMulU64()
7967   const TargetRegisterClass *Src1SubRC =  in splitScalarSMulPseudo()  local
7969   if (RI.isSGPRClass(Src1SubRC))  in splitScalarSMulPseudo()
7970     Src1SubRC = RI.getEquivalentVGPRClass(Src1SubRC);  in splitScalarSMulPseudo()
7977       buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);  in splitScalarSMulPseudo()
8032   const TargetRegisterClass *Src1SubRC =  in splitScalar64BitBinaryOp()  local
8038                                                        AMDGPU::sub0, Src1SubRC);  in splitScalar64BitBinaryOp()
8042                                                        AMDGPU::sub1, Src1SubRC);  in splitScalar64BitBinaryOp()