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Searched refs:Src0SubRC (Results 1 – 2 of 2) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp7792 const TargetRegisterClass *Src0SubRC = in splitScalar64BitUnaryOp() local
7796 AMDGPU::sub0, Src0SubRC); in splitScalar64BitUnaryOp()
7807 AMDGPU::sub1, Src0SubRC); in splitScalar64BitUnaryOp()
7854 const TargetRegisterClass *Src0SubRC = in splitScalarSMulU64() local
7856 if (RI.isSGPRClass(Src0SubRC)) in splitScalarSMulU64()
7857 Src0SubRC = RI.getEquivalentVGPRClass(Src0SubRC); in splitScalarSMulU64()
7866 buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC); in splitScalarSMulU64()
7870 buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC); in splitScalarSMulU64()
7963 const TargetRegisterClass *Src0SubRC = in splitScalarSMulPseudo() local
7965 if (RI.isSGPRClass(Src0SubRC)) in splitScalarSMulPseudo()
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H A DSIISelLowering.cpp5079 const TargetRegisterClass *Src0SubRC = in EmitInstrWithCustomInserter() local
5085 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC); in EmitInstrWithCustomInserter()
5090 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC); in EmitInstrWithCustomInserter()
5306 const TargetRegisterClass *Src0SubRC = in EmitInstrWithCustomInserter() local
5312 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC); in EmitInstrWithCustomInserter()
5317 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC); in EmitInstrWithCustomInserter()