7792   const TargetRegisterClass *Src0SubRC =  in splitScalar64BitUnaryOp()  local
7796                                                        AMDGPU::sub0, Src0SubRC);  in splitScalar64BitUnaryOp()
7807                                                        AMDGPU::sub1, Src0SubRC);  in splitScalar64BitUnaryOp()
7854   const TargetRegisterClass *Src0SubRC =  in splitScalarSMulU64()  local
7856   if (RI.isSGPRClass(Src0SubRC))  in splitScalarSMulU64()
7857     Src0SubRC = RI.getEquivalentVGPRClass(Src0SubRC);  in splitScalarSMulU64()
7866       buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);  in splitScalarSMulU64()
7870       buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);  in splitScalarSMulU64()
7963   const TargetRegisterClass *Src0SubRC =  in splitScalarSMulPseudo()  local
7965   if (RI.isSGPRClass(Src0SubRC))  in splitScalarSMulPseudo()
7966     Src0SubRC = RI.getEquivalentVGPRClass(Src0SubRC);  in splitScalarSMulPseudo()
7975       buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);  in splitScalarSMulPseudo()
8026   const TargetRegisterClass *Src0SubRC =  in splitScalar64BitBinaryOp()  local
8036                                                        AMDGPU::sub0, Src0SubRC);  in splitScalar64BitBinaryOp()
8040                                                        AMDGPU::sub1, Src0SubRC);  in splitScalar64BitBinaryOp()