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Searched refs:Src0RC (Results 1 – 4 of 4) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td1703 class getIns32 <RegisterOperand Src0RC, RegisterOperand Src1RC, int NumSrcArgs> {
1704 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
1705 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1710 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1724 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1727 (ins Src0Mod:$src0_modifiers, Src0RC:$src0, Clamp0:$clamp),
1728 (ins Src0Mod:$src0_modifiers, Src0RC:$src0)))
1732 (ins Src0RC:$src0, Clamp0:$clamp),
1733 (ins Src0RC:$src0))
1739 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
[all …]
H A DSIInstrInfo.cpp6673 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0); in legalizeOperands() local
6674 if (DstRC != Src0RC) { in legalizeOperands()
7788 const TargetRegisterClass *Src0RC = Src0.isReg() ? in splitScalar64BitUnaryOp() local
7793 RI.getSubRegisterClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
7795 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp()
7806 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp()
7852 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg()); in splitScalarSMulU64() local
7855 RI.getSubRegisterClass(Src0RC, AMDGPU::sub0); in splitScalarSMulU64()
7866 buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC); in splitScalarSMulU64()
7870 buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC); in splitScalarSMulU64()
[all …]
H A DAMDGPUInstructionSelector.cpp819 const TargetRegisterClass *Src0RC = in selectG_INSERT() local
826 Src0RC = TRI.getSubClassWithSubReg(Src0RC, SubReg); in selectG_INSERT()
827 if (!Src0RC || !Src1RC) in selectG_INSERT()
831 !RBI.constrainGenericRegister(Src0Reg, *Src0RC, *MRI) || in selectG_INSERT()
H A DSIISelLowering.cpp5072 const TargetRegisterClass *Src0RC = Src0.isReg() in EmitInstrWithCustomInserter() local
5080 TRI->getSubRegisterClass(Src0RC, AMDGPU::sub0); in EmitInstrWithCustomInserter()
5085 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC); in EmitInstrWithCustomInserter()
5090 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC); in EmitInstrWithCustomInserter()
5299 const TargetRegisterClass *Src0RC = Src0.isReg() in EmitInstrWithCustomInserter() local
5307 TRI->getSubRegisterClass(Src0RC, AMDGPU::sub0); in EmitInstrWithCustomInserter()
5312 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC); in EmitInstrWithCustomInserter()
5317 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC); in EmitInstrWithCustomInserter()