6673     const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);  in legalizeOperands()  local
6674     if (DstRC != Src0RC) {  in legalizeOperands()
7788   const TargetRegisterClass *Src0RC = Src0.isReg() ?  in splitScalar64BitUnaryOp()  local
7793       RI.getSubRegisterClass(Src0RC, AMDGPU::sub0);  in splitScalar64BitUnaryOp()
7795   MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,  in splitScalar64BitUnaryOp()
7806   MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,  in splitScalar64BitUnaryOp()
7852   const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());  in splitScalarSMulU64()  local
7855       RI.getSubRegisterClass(Src0RC, AMDGPU::sub0);  in splitScalarSMulU64()
7866       buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);  in splitScalarSMulU64()
7870       buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);  in splitScalarSMulU64()
7961   const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());  in splitScalarSMulPseudo()  local
7964       RI.getSubRegisterClass(Src0RC, AMDGPU::sub0);  in splitScalarSMulPseudo()
7975       buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);  in splitScalarSMulPseudo()
8022   const TargetRegisterClass *Src0RC = Src0.isReg() ?  in splitScalar64BitBinaryOp()  local
8027       RI.getSubRegisterClass(Src0RC, AMDGPU::sub0);  in splitScalar64BitBinaryOp()
8035   MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,  in splitScalar64BitBinaryOp()
8039   MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,  in splitScalar64BitBinaryOp()