Searched refs:ShiftedVal (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 181 uint64_t ShiftedVal = (uint64_t)Val << LeadingZeros; in generateInstSeqLeadingZeros() local
185 ShiftedVal |= maskTrailingOnes<uint64_t>(LeadingZeros); in generateInstSeqLeadingZeros()
188 generateInstSeqImpl(ShiftedVal, STI, TmpSeq); in generateInstSeqLeadingZeros()
198 ShiftedVal &= maskTrailingZeros<uint64_t>(LeadingZeros); in generateInstSeqLeadingZeros()
200 generateInstSeqImpl(ShiftedVal, STI, TmpSeq); in generateInstSeqLeadingZeros()
236 int64_t ShiftedVal = Val >> TrailingZeros; in generateInstSeq() local
242 isInt<6>(ShiftedVal) && !STI.hasFeature(RISCV::TuneLUIADDIFusion); in generateInstSeq()
244 generateInstSeqImpl(ShiftedVal, STI, TmpSeq); in generateInstSeq()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 227 auto ShiftedVal = B.buildShl(Ty, LHS, Shift); in matchAArch64MulConstCombine() local
229 Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal.getReg(0) : LHS; in matchAArch64MulConstCombine()
230 Register AddSubRHS = ShiftValUseIsLHS ? LHS : ShiftedVal.getReg(0); in matchAArch64MulConstCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4456 auto CanShrinkImmediate = [&](int64_t &ShiftedVal) { in tryShrinkShlLogicImm() argument
4460 ShiftedVal = (uint64_t)Val >> ShAmt; in tryShrinkShlLogicImm()
4461 if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal)) in tryShrinkShlLogicImm()
4464 if (ShiftedVal == UINT8_MAX || ShiftedVal == UINT16_MAX) in tryShrinkShlLogicImm()
4467 ShiftedVal = Val >> ShAmt; in tryShrinkShlLogicImm()
4468 if ((!isInt<8>(Val) && isInt<8>(ShiftedVal)) || in tryShrinkShlLogicImm()
4469 (!isInt<32>(Val) && isInt<32>(ShiftedVal))) in tryShrinkShlLogicImm()
4473 ShiftedVal = (uint64_t)Val >> ShAmt; in tryShrinkShlLogicImm()
4474 if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal)) in tryShrinkShlLogicImm()
4480 int64_t ShiftedVal; in tryShrinkShlLogicImm() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1005 if (auto ShiftedVal = getShiftedVal<12>()) in isAddSubImm() local
1006 return ShiftedVal->first >= 0 && ShiftedVal->first <= 0xfff; in isAddSubImm()
1018 if (auto ShiftedVal = getShiftedVal<12>()) in isAddSubImmNeg() local
1019 return ShiftedVal->first < 0 && -ShiftedVal->first <= 0xfff; in isAddSubImmNeg()
1934 if (auto ShiftedVal = getShiftedVal<Shift>()) { in addImmWithOptionalShiftOperands() local
1935 Inst.addOperand(MCOperand::createImm(ShiftedVal->first)); in addImmWithOptionalShiftOperands()
1936 Inst.addOperand(MCOperand::createImm(ShiftedVal->second)); in addImmWithOptionalShiftOperands()
1949 if (auto ShiftedVal = getShiftedVal<Shift>()) { in addImmNegWithOptionalShiftOperands() local
1950 Inst.addOperand(MCOperand::createImm(-ShiftedVal->first)); in addImmNegWithOptionalShiftOperands()
1951 Inst.addOperand(MCOperand::createImm(ShiftedVal->second)); in addImmNegWithOptionalShiftOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/ |
| H A D | InstrProfiling.cpp | 1298 auto *ShiftedVal = Builder.CreateShl(Builder.getInt8(0x1), BitToSet); in lowerMCDCTestVectorBitmapUpdate() local
1300 Builder.Insert(getRMWOrCall(BitmapByteAddr, ShiftedVal)); in lowerMCDCTestVectorBitmapUpdate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 653 int64_t ShiftedVal = Val >> ShAmt; in tryShrinkShlLogicImm() local
654 if (!isInt<12>(ShiftedVal)) in tryShrinkShlLogicImm()
674 CurDAG->getTargetConstant(ShiftedVal, DL, VT)); in tryShrinkShlLogicImm()
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