Searched refs:ShiftedVal (Results 1 – 7 of 7) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 211 uint64_t ShiftedVal = (uint64_t)Val << LeadingZeros; in generateInstSeqLeadingZeros() local
215 ShiftedVal |= maskTrailingOnes<uint64_t>(LeadingZeros); in generateInstSeqLeadingZeros()
218 generateInstSeqImpl(ShiftedVal, STI, TmpSeq); in generateInstSeqLeadingZeros()
228 ShiftedVal &= maskTrailingZeros<uint64_t>(LeadingZeros); in generateInstSeqLeadingZeros()
230 generateInstSeqImpl(ShiftedVal, STI, TmpSeq); in generateInstSeqLeadingZeros()
266 int64_t ShiftedVal = Val >> TrailingZeros; in generateInstSeq() local
272 isInt<6>(ShiftedVal) && !STI.hasFeature(RISCV::TuneLUIADDIFusion); in generateInstSeq()
274 generateInstSeqImpl(ShiftedVal, STI, TmpSeq); in generateInstSeq()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 227 auto ShiftedVal = B.buildShl(Ty, LHS, Shift); in matchAArch64MulConstCombine() local
229 Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal.getReg(0) : LHS; in matchAArch64MulConstCombine()
230 Register AddSubRHS = ShiftValUseIsLHS ? LHS : ShiftedVal.getReg(0); in matchAArch64MulConstCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/ |
| H A D | InstrProfiling.cpp | 1267 auto *ShiftedVal = Builder.CreateShl(Builder.getInt8(0x1), BitToSet); in lowerMCDCTestVectorBitmapUpdate() local
1277 auto *Masked = Builder.CreateAnd(Bitmap, ShiftedVal); in lowerMCDCTestVectorBitmapUpdate()
1278 auto *ShouldStore = Builder.CreateICmpNE(Masked, ShiftedVal); in lowerMCDCTestVectorBitmapUpdate()
1287 Builder.CreateAtomicRMW(AtomicRMWInst::Or, BitmapByteAddr, ShiftedVal, in lowerMCDCTestVectorBitmapUpdate()
1292 auto *Result = Builder.CreateOr(Bitmap, ShiftedVal); in lowerMCDCTestVectorBitmapUpdate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4522 auto CanShrinkImmediate = [&](int64_t &ShiftedVal) { in tryShrinkShlLogicImm() argument
4526 ShiftedVal = (uint64_t)Val >> ShAmt; in tryShrinkShlLogicImm()
4527 if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal)) in tryShrinkShlLogicImm()
4530 if (ShiftedVal == UINT8_MAX || ShiftedVal == UINT16_MAX) in tryShrinkShlLogicImm()
4533 ShiftedVal = Val >> ShAmt; in tryShrinkShlLogicImm()
4534 if ((!isInt<8>(Val) && isInt<8>(ShiftedVal)) || in tryShrinkShlLogicImm()
4535 (!isInt<32>(Val) && isInt<32>(ShiftedVal))) in tryShrinkShlLogicImm()
4539 ShiftedVal = (uint64_t)Val >> ShAmt; in tryShrinkShlLogicImm()
4540 if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal)) in tryShrinkShlLogicImm()
4546 int64_t ShiftedVal; in tryShrinkShlLogicImm() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/DirectX/ |
| H A D | DXILIntrinsicExpansion.cpp | 719 Value *ShiftedVal = Builder.CreateLShr(InputVal, ShiftAmt); in expandBufferStoreIntrinsic() local
720 HighBits = Builder.CreateTrunc(ShiftedVal, SplitElementTy); in expandBufferStoreIntrinsic()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1028 if (auto ShiftedVal = getShiftedVal<12>()) in isAddSubImm() local
1029 return ShiftedVal->first >= 0 && ShiftedVal->first <= 0xfff; in isAddSubImm()
1041 if (auto ShiftedVal = getShiftedVal<12>()) in isAddSubImmNeg() local
1042 return ShiftedVal->first < 0 && -ShiftedVal->first <= 0xfff; in isAddSubImmNeg()
1963 if (auto ShiftedVal = getShiftedVal<Shift>()) { in addImmWithOptionalShiftOperands() local
1964 Inst.addOperand(MCOperand::createImm(ShiftedVal->first)); in addImmWithOptionalShiftOperands()
1965 Inst.addOperand(MCOperand::createImm(ShiftedVal->second)); in addImmWithOptionalShiftOperands()
1978 if (auto ShiftedVal = getShiftedVal<Shift>()) { in addImmNegWithOptionalShiftOperands() local
1979 Inst.addOperand(MCOperand::createImm(-ShiftedVal->first)); in addImmNegWithOptionalShiftOperands()
1980 Inst.addOperand(MCOperand::createImm(ShiftedVal->second)); in addImmNegWithOptionalShiftOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 567 int64_t ShiftedVal = Val >> ShAmt; in tryShrinkShlLogicImm() local
568 if (!isInt<12>(ShiftedVal)) in tryShrinkShlLogicImm()
588 CurDAG->getSignedTargetConstant(ShiftedVal, DL, VT)); in tryShrinkShlLogicImm()
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