| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64Schedule.td | 25 def WriteISReg : SchedWrite; // ALU of Shifted-Reg
28 def ReadISReg : SchedRead; // ALU of Shifted-Reg
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| H A D | AArch64SchedA55.td | 68 def : WriteRes<WriteISReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Shifted-Reg
223 // Shifted operand
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| H A D | AArch64AsmPrinter.cpp | 2250 uint64_t Shifted = UOffset >> BitPos; in LowerMOVaddrPAC() local
2252 return Shifted != 0; in LowerMOVaddrPAC()
2254 if (((Shifted >> I) & 0xffff) != 0xffff) in LowerMOVaddrPAC()
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| H A D | AArch64SchedTSV110.td | 377 // Shifted Register with Shift == 0
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| H A D | AArch64SchedA57.td | 144 // Shifted Register with Shift == 0
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| H A D | AArch64SchedAmpere1.td | 591 } // ALU of Shifted-Reg
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| H A D | AArch64SchedAmpere1B.td | 547 } // ALU of Shifted-Reg
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| H A D | AArch64SchedA510.td | 70 def : WriteRes<WriteISReg, [CortexA510UnitALU]> { let Latency = 2; } // ALU of Shifted-Reg
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| H A D | AArch64ISelLowering.cpp | 15257 SDValue Shifted = in getVectorBitwiseReduce() local
15259 Scalar = DAG.getNode(ScalarOpcode, DL, ScalarVT, Scalar, Shifted); in getVectorBitwiseReduce()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 2929 unsigned Shifted = 0; in alignToARMConstant() local
2936 Shifted += 2; in alignToARMConstant()
2945 if (Shifted > 24) in alignToARMConstant()
2946 Value = Value >> (Shifted - 24); in alignToARMConstant()
2948 Value = Value << (24 - Shifted); in alignToARMConstant()
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| H A D | ARMScheduleM7.td | 322 // Shifted ALU operands are read a cycle early.
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| H A D | ARMInstrThumb2.td | 54 // Shifted operands. No register controlled shifts for Thumb2.
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 2224 Value *Shifted = IC.Builder.CreateLShr(Masked, ShiftAmt); in instCombineIntrinsic() local
2225 return IC.replaceInstUsesWith(II, Shifted); in instCombineIntrinsic()
2267 Value *Shifted = IC.Builder.CreateShl(Input, ShiftAmt); in instCombineIntrinsic() local
2268 Value *Masked = IC.Builder.CreateAnd(Shifted, II.getArgOperand(1)); in instCombineIntrinsic()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVectorCombine.cpp | 1852 Value *Shifted = Op.X.Sgn == Signed || Op.Y.Sgn == Signed in processFxpMulChopped() local
1855 return Builder.CreateTrunc(Shifted, InpTy, "trn"); in processFxpMulChopped()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ScalarEvolution.cpp | 5939 const SCEV *Shifted = SCEVShiftRewriter::rewrite(BEValue, L, *this); in createAddRecFromPHI() local
5940 const SCEV *Start = SCEVInitRewriter::rewrite(Shifted, L, *this, false); in createAddRecFromPHI()
5941 if (Shifted != getCouldNotCompute() && in createAddRecFromPHI()
5949 insertValueToMap(PN, Shifted); in createAddRecFromPHI()
5950 return Shifted; in createAddRecFromPHI()
13365 const SCEV *Shifted = SE.getAddRecExpr(Operands, getLoop(), in getNumIterationsInRange() local
13367 if (const auto *ShiftedAddRec = dyn_cast<SCEVAddRecExpr>(Shifted)) in getNumIterationsInRange()
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| /freebsd/contrib/llvm-project/clang/lib/Format/ |
| H A D | Format.cpp | 3593 auto Shifted = tooling::Replacement(FileName, NewOffset, 0, in fixCppIncludeInsertions() local
3595 Result = Result.merge(tooling::Replacements(Shifted)); in fixCppIncludeInsertions()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3843 auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt); in lower() local
3844 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted); in lower()
8287 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); in lowerSMULH_UMULH() local
8288 MIRBuilder.buildTrunc(Result, Shifted); in lowerSMULH_UMULH()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | SimplifyCFG.cpp | 6876 Value *Shifted = Builder.CreateLShr(TableMask, MaskIndex, "switch.shifted"); in SwitchToLookupTable() local
6878 Shifted, Type::getInt1Ty(Mod.getContext()), "switch.lobit"); in SwitchToLookupTable()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchInstrInfo.td | 1344 /// Shifted addition
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 12083 SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT, in lowerGET_ROUNDING()
12085 SDValue Masked = DAG.getNode(ISD::AND, DL, XLenVT, Shifted, in lowerGET_ROUNDING()
12115 SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT, in lowerSET_ROUNDING()
12117 RMValue = DAG.getNode(ISD::AND, DL, XLenVT, Shifted, in lowerSET_ROUNDING()
12081 SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT, lowerGET_ROUNDING() local
12113 SDValue Shifted = DAG.getNode(ISD::SRL, DL, XLenVT, lowerSET_ROUNDING() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 14018 auto Shifted = DAG.getNode(ISD::SRL, DL, MVT::i64, SubNode, in generateEquivalentSub() local
14020 auto Final = Shifted; in generateEquivalentSub()
14024 Final = DAG.getNode(ISD::XOR, DL, MVT::i64, Shifted, in generateEquivalentSub()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 10710 SDValue Shifted = in expandFixedPointMul() local
10713 Hi = DAG.getNode(ISD::TRUNCATE, dl, VT, Shifted); in expandFixedPointMul()
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| H A D | DAGCombiner.cpp | 653 SDValue MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
8301 SDValue DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos, in MatchRotatePosNeg() argument
8313 EVT VT = Shifted.getValueType(); in MatchRotatePosNeg()
8316 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted, in MatchRotatePosNeg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 14619 SDValue Shifted = DAG.getZExtOrTrunc(Shift.getOperand(0), in performCvtF32UByteNCombine() local
14630 MVT::f32, Shifted); in performCvtF32UByteNCombine()
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| /freebsd/contrib/ncurses/misc/ |
| H A D | terminfo.src | 2156 # Shifted f1-f12 give cons25 codes, rather than xterm function-keys
2481 # Scroll 0-Jump Shifted 3 0-#
4246 # Shifted F1 is F11. F13-F20 inherit from the defaults, and the last distinct
7583 # Shifted cursor-keys send nothing, but xterm modifiers for control+shift
11242 # Shifted Function Keys:
14872 # 1= Shifted
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