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Searched refs:ShiftVal (Results 1 – 25 of 28) sorted by relevance

12

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp297 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue() local
298 assert((ShiftVal == 0 || ShiftVal == 12) && in getAddSubImmOpValue()
301 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getAddSubImmOpValue()
317 ShiftVal = 12; in getAddSubImmOpValue()
319 return ShiftVal == 0 ? 0 : (1 << ShiftVal); in getAddSubImmOpValue()
662 unsigned ShiftVal = AArch64_AM::getShiftValue(ShiftOpnd); in getImm8OptLsl() local
663 assert((ShiftVal == 0 || ShiftVal == 8) && in getImm8OptLsl()
668 return (Immediate & 0xff) | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getImm8OptLsl()
689 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm()); in getMoveVecShifterOpValue() local
690 assert((ShiftVal == 8 || ShiftVal == 16) && "Invalid shift amount!"); in getMoveVecShifterOpValue()
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H A DAArch64InstPrinter.cpp1290 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); in printArithExtend() local
1302 if (ShiftVal != 0) { in printArithExtend()
1304 markup(O, Markup::Immediate) << "#" << ShiftVal; in printArithExtend()
1310 if (ShiftVal != 0) { in printArithExtend()
1312 markup(O, Markup::Immediate) << "#" << ShiftVal; in printArithExtend()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp547 for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) { in getIntMatCost() local
548 APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize); in getIntMatCost()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/
H A DX86.cpp1701 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local
1709 if (ShiftVal >= 32) in EmitX86BuiltinExpr()
1714 if (ShiftVal > 16) { in EmitX86BuiltinExpr()
1715 ShiftVal -= 16; in EmitX86BuiltinExpr()
1724 unsigned Idx = ShiftVal + i; in EmitX86BuiltinExpr()
1742 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local
1745 ShiftVal &= NumElts - 1; in EmitX86BuiltinExpr()
1749 Indices[i] = i + ShiftVal; in EmitX86BuiltinExpr()
1825 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[1])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local
1831 if (ShiftVal >= 16) in EmitX86BuiltinExpr()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h341 bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal) const;
342 void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal) const;
360 unsigned &ShiftVal) const;
362 const unsigned &ShiftVal) const;
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DDXILEmitter.cpp570 int ShiftVal = 1; in emitDXILOperationTableDataStructs() local
582 OS << " " << Name << " = 1 << " << std::to_string(ShiftVal++) << ",\n"; in emitDXILOperationTableDataStructs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1248 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitAddSub() local
1253 ShiftVal, SetFlags, WantResult); in emitAddSub()
1270 uint64_t ShiftVal = C->getZExtValue(); in emitAddSub() local
1276 ShiftVal, SetFlags, WantResult); in emitAddSub()
1619 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitLogicalOp() local
1624 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal); in emitLogicalOp()
1634 uint64_t ShiftVal = C->getZExtValue(); in emitLogicalOp() local
1638 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal); in emitLogicalOp()
4674 uint64_t ShiftVal = C->getValue().logBase2(); in selectMul() local
4701 Register ResultReg = emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt); in selectMul()
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H A DAArch64ISelDAGToDAG.cpp682 unsigned ShiftVal = CSD->getZExtValue(); in isWorthFoldingSHL() local
683 if (ShiftVal > 3) in isWorthFoldingSHL()
944 unsigned ShiftVal = 0; in SelectArithExtendedRegister() local
951 ShiftVal = CSD->getZExtValue(); in SelectArithExtendedRegister()
952 if (ShiftVal > 4) in SelectArithExtendedRegister()
988 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N), in SelectArithExtendedRegister()
997 unsigned ShiftVal = 0; in SelectArithUXTXRegister() local
1006 ShiftVal = CSD->getZExtValue(); in SelectArithUXTXRegister()
1007 if (ShiftVal > 4) in SelectArithUXTXRegister()
1012 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N), in SelectArithUXTXRegister()
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H A DAArch64InstrInfo.cpp1042 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
1043 if (ShiftVal == 0) in isFalkorShiftExtFast()
1045 return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5; in isFalkorShiftExtFast()
1069 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
1070 return ShiftVal == 0 || in isFalkorShiftExtFast()
1071 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 31); in isFalkorShiftExtFast()
1077 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
1078 return ShiftVal == 0 || in isFalkorShiftExtFast()
1079 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 63); in isFalkorShiftExtFast()
H A DAArch64TargetTransformInfo.cpp407 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
408 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2808 auto ShiftVal = Op.getOperand(1); in LowerShift() local
2837 ShiftVal = SkipImpliedMask(ShiftVal, LaneBits - 1); in LowerShift()
2838 ShiftVal = DAG.getSplatValue(ShiftVal); in LowerShift()
2839 if (!ShiftVal) in LowerShift()
2843 ShiftVal = SkipImpliedMask(ShiftVal, LaneBits - 1); in LowerShift()
2845 ShiftVal = DAG.getAnyExtOrTrunc(ShiftVal, DL, MVT::i32); in LowerShift()
2862 return DAG.getNode(Opcode, DL, Op.getValueType(), Op.getOperand(0), ShiftVal); in LowerShift()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMParallelDSP.cpp788 Value *ShiftVal = ConstantInt::get(LoadTy, OffsetTy->getBitWidth()); in CreateWideLoad() local
789 Value *Top = IRB.CreateLShr(WideLoad, ShiftVal); in CreateWideLoad()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1960 auto matchFirstShift = [&](const MachineInstr *MI, uint64_t &ShiftVal) { in matchShiftOfShiftedLogic() argument
1972 ShiftVal = MaybeImmVal->Value.getSExtValue(); in matchShiftOfShiftedLogic()
2078 unsigned &ShiftVal) const { in matchCombineMulToShl()
2085 ShiftVal = MaybeImmVal->Value.exactLogBase2(); in matchCombineMulToShl()
2086 return (static_cast<int32_t>(ShiftVal) != -1); in matchCombineMulToShl()
2090 unsigned &ShiftVal) const { in applyCombineMulToShl()
2094 auto ShiftCst = MIB.buildConstant(ShiftTy, ShiftVal); in applyCombineMulToShl()
2098 if (ShiftVal == ShiftTy.getScalarSizeInBits() - 1) in applyCombineMulToShl()
2404 unsigned &ShiftVal) const { in matchCombineShiftToUnmerge()
2423 ShiftVal = MaybeImmVal->Value.getSExtValue(); in matchCombineShiftToUnmerge()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp419 ConstantInt *ShiftVal = nullptr; in foldVecTruncToExtElt() local
422 m_ConstantInt(ShiftVal)))) || in foldVecTruncToExtElt()
429 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt()
H A DInstCombineCompares.cpp2328 const APInt *ShiftVal; in foldICmpShlConstant() local
2329 if (Cmp.isEquality() && match(Shl->getOperand(0), m_APInt(ShiftVal))) in foldICmpShlConstant()
2330 return foldICmpShlConstConst(Cmp, Shl->getOperand(1), C, *ShiftVal); in foldICmpShlConstant()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3086 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) { in isSimpleShift() argument
3095 ShiftVal = Amount; in isSimpleShift()
3264 unsigned NewCCMask, ShiftVal; in adjustForTestUnderMask() local
3267 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
3268 (MaskVal >> ShiftVal != 0) && in adjustForTestUnderMask()
3269 ((CmpVal >> ShiftVal) << ShiftVal) == CmpVal && in adjustForTestUnderMask()
3271 MaskVal >> ShiftVal, in adjustForTestUnderMask()
3272 CmpVal >> ShiftVal, in adjustForTestUnderMask()
3275 MaskVal >>= ShiftVal; in adjustForTestUnderMask()
3278 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp2430 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
2435 ReplaceNode(N, getBFE32(false, SDLoc(N), Srl.getOperand(0), ShiftVal, in SelectS_BFE()
2451 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
2452 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal; in SelectS_BFE()
2456 ReplaceNode(N, getBFE32(false, SDLoc(N), And.getOperand(0), ShiftVal, in SelectS_BFE()
H A DSIISelLowering.cpp12920 auto ShiftVal = 32 * (DWordOffset % (ScalarTySize / 32)); in getDWordFromOffset() local
12921 if (ShiftVal) in getDWordFromOffset()
12923 DAG.getConstant(ShiftVal, SL, MVT::i32)); in getDWordFromOffset()
12947 auto ShiftVal = 32 * DWordOffset; in getDWordFromOffset() local
12949 DAG.getConstant(ShiftVal, SL, MVT::i32)); in getDWordFromOffset()
14481 ConstantSDNode *ShiftVal = dyn_cast<ConstantSDNode>(MulLHS.getOperand(1)); in tryFoldMADwithSRL() local
14482 if (!ShiftVal || ShiftVal->getAsZExtVal() != 32 || in tryFoldMADwithSRL()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp7179 const APInt ShiftVal = ValAndVeg->Value; in isWorthFoldingIntoAddrMode() local
7182 return !(STI.hasAddrLSLSlow14() && (ShiftVal == 1 || ShiftVal == 4)); in isWorthFoldingIntoAddrMode()
7757 unsigned ShiftVal = AArch64_AM::getShifterImm(ShType, Val); in selectShiftedRegister() local
7760 [=](MachineInstrBuilder &MIB) { MIB.addImm(ShiftVal); }}}; in selectShiftedRegister()
7848 uint64_t ShiftVal = 0; in selectArithExtendedRegister() local
7865 ShiftVal = *MaybeShiftVal; in selectArithExtendedRegister()
7866 if (ShiftVal > 4) in selectArithExtendedRegister()
7902 MIB.addImm(getArithExtendImm(Ext, ShiftVal)); in selectArithExtendedRegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp5361 unsigned ShiftVal = 0; in Select() local
5366 ShiftVal = 1; in Select()
5370 ShiftVal = 1; in Select()
5375 ShiftVal = 3; in Select()
5379 ShiftVal = 3; in Select()
5384 ShiftVal = 2; in Select()
5388 ShiftVal = 2; in Select()
5420 SDValue Ops[] = {Move, getI32Imm((32 - (4 + ShiftVal)) & 31, dl), in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1999 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
2015 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal); in selectShift()
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DAutoUpgrade.cpp1799 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); in upgradeX86ALIGNIntrinsics() local
1808 ShiftVal &= (NumElts - 1); in upgradeX86ALIGNIntrinsics()
1812 if (ShiftVal >= 32) in upgradeX86ALIGNIntrinsics()
1817 if (ShiftVal > 16) { in upgradeX86ALIGNIntrinsics()
1818 ShiftVal -= 16; in upgradeX86ALIGNIntrinsics()
1827 unsigned Idx = ShiftVal + i; in upgradeX86ALIGNIntrinsics()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp384 APInt ShiftVal = COp->getValue(); in simplifyX86varShift() local
385 if (ShiftVal.uge(BitWidth)) { in simplifyX86varShift()
391 ShiftAmts.push_back((int)ShiftVal.getZExtValue()); in simplifyX86varShift()
H A DX86ISelLowering.cpp6520 uint64_t ShiftVal = N.getConstantOperandVal(1); in getFauxShuffleMask() local
6522 if (NumBitsPerElt <= ShiftVal) { in getFauxShuffleMask()
6528 if ((ShiftVal % 8) != 0) in getFauxShuffleMask()
6531 uint64_t ByteShift = ShiftVal / 8; in getFauxShuffleMask()
7121 SDValue ShiftVal = DAG.getTargetConstant(NumBits / 8, dl, MVT::i8); in getVShift() local
7122 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal)); in getVShift()
18807 int ShiftVal = (IdxVal % 4) * 8; in LowerEXTRACT_VECTOR_ELT() local
18808 if (ShiftVal != 0) in LowerEXTRACT_VECTOR_ELT()
18810 DAG.getConstant(ShiftVal, dl, MVT::i8)); in LowerEXTRACT_VECTOR_ELT()
18819 int ShiftVal = (IdxVal % 2) * 8; in LowerEXTRACT_VECTOR_ELT() local
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H A DX86TargetTransformInfo.cpp5976 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
5977 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()

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