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Searched refs:ShiftVal (Results 1 – 25 of 26) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp289 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()
290 assert((ShiftVal == 0 || ShiftVal == 12) && in getAddSubImmOpValue()
293 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getAddSubImmOpValue()
310 ShiftVal = 12;
312 return ShiftVal == 0 ? 0 : (1 << ShiftVal); in getCondBranchTargetOpValue()
629 unsigned ShiftVal = AArch64_AM::getShiftValue(ShiftOpnd); in getMoveVecShifterOpValue()
630 assert((ShiftVal in getMoveVecShifterOpValue()
283 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); getAddSubImmOpValue() local
600 unsigned ShiftVal = AArch64_AM::getShiftValue(ShiftOpnd); getImm8OptLsl() local
627 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm()); getMoveVecShifterOpValue() local
[all...]
H A DAArch64InstPrinter.cpp1277 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); in printArithExtend()
1289 if (ShiftVal != 0) { in printMemExtendImpl()
1291 markup(O, Markup::Immediate) << "#" << ShiftVal; in printMemExtendImpl()
1297 if (ShiftVal != 0) { in printMemExtendImpl()
1299 markup(O, Markup::Immediate) << "#" << ShiftVal; in printMemExtendImpl()
1264 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); printArithExtend() local
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp511 for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) { in getIntMatCost() local
512 APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize); in getIntMatCost()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h314 bool matchCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
315 void applyCombineMulToShl(MachineInstr &MI, unsigned &ShiftVal);
329 unsigned &ShiftVal);
330 void applyCombineShiftToUnmerge(MachineInstr &MI, const unsigned &ShiftVal);
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2400 auto ShiftVal = Op.getOperand(1); in LowerShift() local
2429 ShiftVal = SkipImpliedMask(ShiftVal, LaneBits - 1); in LowerShift()
2430 ShiftVal = DAG.getSplatValue(ShiftVal); in LowerShift()
2431 if (!ShiftVal) in LowerShift()
2435 ShiftVal = SkipImpliedMask(ShiftVal, LaneBits - 1); in LowerShift()
2437 ShiftVal = DAG.getAnyExtOrTrunc(ShiftVal, DL, MVT::i32); in LowerShift()
2454 return DAG.getNode(Opcode, DL, Op.getValueType(), Op.getOperand(0), ShiftVal); in LowerShift()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1253 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitAddSub() local
1258 ShiftVal, SetFlags, WantResult); in emitAddSub()
1275 uint64_t ShiftVal = C->getZExtValue(); in emitAddSub() local
1281 ShiftVal, SetFlags, WantResult); in emitAddSub()
1622 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2(); in emitLogicalOp() local
1627 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal); in emitLogicalOp()
1637 uint64_t ShiftVal = C->getZExtValue(); in emitLogicalOp() local
1641 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal); in emitLogicalOp()
4671 uint64_t ShiftVal = C->getValue().logBase2(); in selectMul() local
4699 emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt); in selectMul()
[all …]
H A DAArch64ISelDAGToDAG.cpp678 unsigned ShiftVal = CSD->getZExtValue(); in isWorthFoldingSHL() local
679 if (ShiftVal > 3) in isWorthFoldingSHL()
940 unsigned ShiftVal = 0; in SelectArithExtendedRegister() local
947 ShiftVal = CSD->getZExtValue(); in SelectArithExtendedRegister()
948 if (ShiftVal > 4) in SelectArithExtendedRegister()
984 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N), in SelectArithExtendedRegister()
993 unsigned ShiftVal = 0; in SelectArithUXTXRegister() local
1002 ShiftVal = CSD->getZExtValue(); in SelectArithUXTXRegister()
1003 if (ShiftVal > 4) in SelectArithUXTXRegister()
1008 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N), in SelectArithUXTXRegister()
[all …]
H A DAArch64InstrInfo.cpp940 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
941 if (ShiftVal == 0) in isFalkorShiftExtFast()
943 return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5; in isFalkorShiftExtFast()
967 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
968 return ShiftVal == 0 || in isFalkorShiftExtFast()
969 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 31); in isFalkorShiftExtFast()
975 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast() local
976 return ShiftVal == 0 || in isFalkorShiftExtFast()
977 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 63); in isFalkorShiftExtFast()
H A DAArch64TargetTransformInfo.cpp374 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
375 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMParallelDSP.cpp783 Value *ShiftVal = ConstantInt::get(LoadTy, OffsetTy->getBitWidth()); in CreateWideLoad() local
784 Value *Top = IRB.CreateLShr(WideLoad, ShiftVal); in CreateWideLoad()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1892 auto matchFirstShift = [&](const MachineInstr *MI, uint64_t &ShiftVal) { in matchShiftOfShiftedLogic() argument
1904 ShiftVal = MaybeImmVal->Value.getSExtValue(); in matchShiftOfShiftedLogic()
2009 unsigned &ShiftVal) { in matchCombineMulToShl() argument
2016 ShiftVal = MaybeImmVal->Value.exactLogBase2(); in matchCombineMulToShl()
2017 return (static_cast<int32_t>(ShiftVal) != -1); in matchCombineMulToShl()
2021 unsigned &ShiftVal) { in applyCombineMulToShl() argument
2025 auto ShiftCst = MIB.buildConstant(ShiftTy, ShiftVal); in applyCombineMulToShl()
2303 unsigned &ShiftVal) { in matchCombineShiftToUnmerge() argument
2322 ShiftVal = MaybeImmVal->Value.getSExtValue(); in matchCombineShiftToUnmerge()
2323 return ShiftVal >= Size / 2 && ShiftVal < Size; in matchCombineShiftToUnmerge()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2738 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) { in isSimpleShift() argument
2747 ShiftVal = Amount; in isSimpleShift()
2916 unsigned NewCCMask, ShiftVal; in adjustForTestUnderMask() local
2919 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
2920 (MaskVal >> ShiftVal != 0) && in adjustForTestUnderMask()
2921 ((CmpVal >> ShiftVal) << ShiftVal) == CmpVal && in adjustForTestUnderMask()
2923 MaskVal >> ShiftVal, in adjustForTestUnderMask()
2924 CmpVal >> ShiftVal, in adjustForTestUnderMask()
2927 MaskVal >>= ShiftVal; in adjustForTestUnderMask()
2930 isSimpleShift(NewC.Op0, ShiftVal) && in adjustForTestUnderMask()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp409 ConstantInt *ShiftVal = nullptr; in foldVecTruncToExtElt() local
412 m_ConstantInt(ShiftVal)))) || in foldVecTruncToExtElt()
419 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt()
H A DInstCombineCompares.cpp2277 const APInt *ShiftVal; in foldICmpShlConstant() local
2278 if (Cmp.isEquality() && match(Shl->getOperand(0), m_APInt(ShiftVal))) in foldICmpShlConstant()
2279 return foldICmpShlConstConst(Cmp, Shl->getOperand(1), C, *ShiftVal); in foldICmpShlConstant()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp2315 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
2320 ReplaceNode(N, getBFE32(false, SDLoc(N), Srl.getOperand(0), ShiftVal, in SelectS_BFE()
2336 uint32_t ShiftVal = Shift->getZExtValue(); in SelectS_BFE() local
2337 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal; in SelectS_BFE()
2341 ReplaceNode(N, getBFE32(false, SDLoc(N), And.getOperand(0), ShiftVal, in SelectS_BFE()
H A DSIISelLowering.cpp12150 auto ShiftVal = 32 * (DWordOffset % (ScalarTySize / 32)); in getDWordFromOffset() local
12151 if (ShiftVal) in getDWordFromOffset()
12153 DAG.getConstant(ShiftVal, SL, MVT::i32)); in getDWordFromOffset()
12177 auto ShiftVal = 32 * DWordOffset; in getDWordFromOffset() local
12179 DAG.getConstant(ShiftVal, SL, MVT::i32)); in getDWordFromOffset()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp7006 const APInt ShiftVal = ValAndVeg->Value; in isWorthFoldingIntoAddrMode() local
7009 return !(STI.hasAddrLSLSlow14() && (ShiftVal == 1 || ShiftVal == 4)); in isWorthFoldingIntoAddrMode()
7579 unsigned ShiftVal = AArch64_AM::getShifterImm(ShType, Val); in selectShiftedRegister() local
7582 [=](MachineInstrBuilder &MIB) { MIB.addImm(ShiftVal); }}}; in selectShiftedRegister()
7670 uint64_t ShiftVal = 0; in selectArithExtendedRegister() local
7687 ShiftVal = *MaybeShiftVal; in selectArithExtendedRegister()
7688 if (ShiftVal > 4) in selectArithExtendedRegister()
7724 MIB.addImm(getArithExtendImm(Ext, ShiftVal)); in selectArithExtendedRegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp5347 unsigned ShiftVal = 0; in Select() local
5352 ShiftVal = 1; in Select()
5356 ShiftVal = 1; in Select()
5361 ShiftVal = 3; in Select()
5365 ShiftVal = 3; in Select()
5370 ShiftVal = 2; in Select()
5374 ShiftVal = 2; in Select()
5406 SDValue Ops[] = {Move, getI32Imm((32 - (4 + ShiftVal)) & 31, dl), in Select()
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DAutoUpgrade.cpp1612 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); in upgradeX86ALIGNIntrinsics() local
1621 ShiftVal &= (NumElts - 1); in upgradeX86ALIGNIntrinsics()
1625 if (ShiftVal >= 32) in upgradeX86ALIGNIntrinsics()
1630 if (ShiftVal > 16) { in upgradeX86ALIGNIntrinsics()
1631 ShiftVal -= 16; in upgradeX86ALIGNIntrinsics()
1640 unsigned Idx = ShiftVal + i; in upgradeX86ALIGNIntrinsics()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1984 uint64_t ShiftVal = C->getZExtValue(); in selectShift() local
2000 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal); in selectShift()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp390 APInt ShiftVal = COp->getValue(); in simplifyX86varShift() local
391 if (ShiftVal.uge(BitWidth)) { in simplifyX86varShift()
397 ShiftAmts.push_back((int)ShiftVal.getZExtValue()); in simplifyX86varShift()
H A DX86ISelLowering.cpp6170 uint64_t ShiftVal = N.getConstantOperandVal(1); in getFauxShuffleMask() local
6172 if (NumBitsPerElt <= ShiftVal) { in getFauxShuffleMask()
6178 if ((ShiftVal % 8) != 0) in getFauxShuffleMask()
6181 uint64_t ByteShift = ShiftVal / 8; in getFauxShuffleMask()
6770 SDValue ShiftVal = DAG.getTargetConstant(NumBits / 8, dl, MVT::i8); in getVShift() local
6771 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal)); in getVShift()
18124 int ShiftVal = (IdxVal % 4) * 8; in LowerEXTRACT_VECTOR_ELT() local
18125 if (ShiftVal != 0) in LowerEXTRACT_VECTOR_ELT()
18127 DAG.getConstant(ShiftVal, dl, MVT::i8)); in LowerEXTRACT_VECTOR_ELT()
18136 int ShiftVal = (IdxVal % 2) * 8; in LowerEXTRACT_VECTOR_ELT() local
[all …]
H A DX86TargetTransformInfo.cpp5642 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) { in getIntImmCost() local
5643 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64); in getIntImmCost()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp15326 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local
15334 if (ShiftVal >= 32) in EmitX86BuiltinExpr()
15339 if (ShiftVal > 16) { in EmitX86BuiltinExpr()
15340 ShiftVal -= 16; in EmitX86BuiltinExpr()
15349 unsigned Idx = ShiftVal + i; in EmitX86BuiltinExpr()
15367 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local
15370 ShiftVal &= NumElts - 1; in EmitX86BuiltinExpr()
15374 Indices[i] = i + ShiftVal; in EmitX86BuiltinExpr()
15450 unsigned ShiftVal = cast<llvm::ConstantInt>(Ops[1])->getZExtValue() & 0xff; in EmitX86BuiltinExpr() local
15456 if (ShiftVal >= 16) in EmitX86BuiltinExpr()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1572 SDValue ShiftVal = DAG.getNode(ISD::SRL, dl, ElementType, StVal, in LowerUnalignedStoreParam() local
1576 ShiftVal, InGlue}; in LowerUnalignedStoreParam()
3377 SDValue ShiftVal = DAG.getNode(ISD::SRL, dl, ElementType, RetVal, in LowerUnalignedStoreRet() local
3380 ShiftVal}; in LowerUnalignedStoreRet()

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