Searched refs:ShiftReg (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 1494 Register ShiftReg = RI.createVirtualRegister(RC); in EmitShiftInstr() local
1514 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) in EmitShiftInstr()
1525 .addReg(ShiftReg) in EmitShiftInstr()
1526 .addReg(ShiftReg); in EmitShiftInstr()
1529 .addReg(ShiftReg); in EmitShiftInstr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1847 Register ShiftReg = RI.createVirtualRegister(RC); in insertShift() local
1859 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg); in insertShift()
1861 ShiftMI.addReg(ShiftReg); in insertShift()
1869 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg) in insertShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 913 unsigned ShiftReg; member
1420 RegShiftedReg.ShiftReg); in isRegShiftedReg()
2609 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
3717 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, SMLoc E, in CreateShiftedRegister() argument
3722 Op->RegShiftedReg.ShiftReg = ShiftReg; in CreateShiftedRegister()
4077 << RegName(RegShiftedReg.ShiftReg) << ">"; in print()
4318 int ShiftReg = 0; in tryParseShiftRegister() local
4323 ShiftReg = SrcReg; in tryParseShiftRegister()
4358 ShiftReg = tryParseRegister(); in tryParseShiftRegister()
4359 if (ShiftReg == -1) { in tryParseShiftRegister()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 1980 Register ShiftReg = Shl.getReg(2); in matchCommuteShift() local
1993 !mi_match(ShiftReg, MRI, m_ICstOrSplat(C2Val))) in matchCommuteShift()
2001 auto S1 = B.buildShl(SrcTy, X, ShiftReg); in matchCommuteShift()
2002 auto S2 = B.buildShl(SrcTy, C1, ShiftReg); in matchCommuteShift()
6511 Register ShiftReg = MI.getOperand(2).getReg(); in matchShiftsTooBig() local
6517 return matchUnaryPredicate(MRI, ShiftReg, IsShiftTooBig); in matchShiftsTooBig()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3077 Register ShiftReg = I.getOperand(2).getReg(); in select() local
3078 const LLT ShiftTy = MRI.getType(ShiftReg); in select()
3085 .addReg(ShiftReg, 0, AArch64::sub_32); in select()
7575 Register ShiftReg = ShiftLHS.getReg(); in selectShiftedRegister() local
7577 unsigned NumBits = MRI.getType(ShiftReg).getSizeInBits(); in selectShiftedRegister()
7581 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ShiftReg); }, in selectShiftedRegister()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 12269 Register ShiftReg = in EmitPartwordAtomicBinary() local
12325 BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg) in EmitPartwordAtomicBinary()
12339 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg).addReg(incr).addReg(ShiftReg); in EmitPartwordAtomicBinary()
12350 .addReg(ShiftReg); in EmitPartwordAtomicBinary()
12378 .addReg(ShiftReg); in EmitPartwordAtomicBinary()
12418 .addReg(ShiftReg); in EmitPartwordAtomicBinary()
13281 Register ShiftReg = in EmitInstrWithCustomInserter() local
13344 BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg) in EmitInstrWithCustomInserter()
13360 .addReg(ShiftReg); in EmitInstrWithCustomInserter()
13363 .addReg(ShiftReg); in EmitInstrWithCustomInserter()
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