Lines Matching refs:ShiftReg
913 unsigned ShiftReg; member
1420 RegShiftedReg.ShiftReg); in isRegShiftedReg()
2609 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
3717 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, SMLoc E, in CreateShiftedRegister() argument
3722 Op->RegShiftedReg.ShiftReg = ShiftReg; in CreateShiftedRegister()
4077 << RegName(RegShiftedReg.ShiftReg) << ">"; in print()
4318 int ShiftReg = 0; in tryParseShiftRegister() local
4323 ShiftReg = SrcReg; in tryParseShiftRegister()
4358 ShiftReg = tryParseRegister(); in tryParseShiftRegister()
4359 if (ShiftReg == -1) { in tryParseShiftRegister()
4370 if (ShiftReg && ShiftTy != ARM_AM::rrx) in tryParseShiftRegister()
4372 ShiftTy, SrcReg, ShiftReg, Imm, S, EndLoc, *this)); in tryParseShiftRegister()