Searched refs:ShiftR (Results 1 – 5 of 5) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | ScaledNumber.h | 314 int32_t ShiftR = ScaleDiff - ShiftL; in matchScales() local
315 if (ShiftR >= getWidth<DigitsT>()) { in matchScales()
322 RDigits >>= ShiftR; in matchScales()
325 RScale += ShiftR; in matchScales()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 1446 int ShiftR = SMA.MinSrc; in packs() local
1447 if (ShiftR >= static_cast<int>(HwLen)) { in packs()
1450 ShiftR -= HwLen; in packs()
1452 OpRef RetVal = valign(Va, Vb, ShiftR, Ty, Results); in packs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 3718 SDValue ShiftR = in get64BitZExtCompare() local
3725 ShiftR, ShiftL, SubtractCarry), 0); in get64BitZExtCompare()
3873 SDValue ShiftR = in get64BitSExtCompare() local
3885 ShiftR, ShiftL, SubtractCarry), 0); in get64BitSExtCompare()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 2590 auto ShiftR = IsShift ? RHS : MIRBuilder.buildShl(WideTy, RHS, ShiftK); in widenScalarAddSubShlSat() local
2593 {ShiftL, ShiftR}, MI.getFlags()); in widenScalarAddSubShlSat()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 30225 SDValue ShiftR = Op->getOperand(0); in SimplifyDemandedBitsForTargetNode() local
30226 if (ShiftR->getOpcode() != AArch64ISD::VLSHR) in SimplifyDemandedBitsForTargetNode()
30229 if (!ShiftL.hasOneUse() || !ShiftR.hasOneUse()) in SimplifyDemandedBitsForTargetNode()
30233 unsigned ShiftRBits = ShiftR->getConstantOperandVal(1); in SimplifyDemandedBitsForTargetNode()
30251 return TLO.CombineTo(Op, ShiftR->getOperand(0)); in SimplifyDemandedBitsForTargetNode()
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