| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 816 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); in printShiftImmOperand() local
817 bool isASR = (ShiftOp & (1 << 5)) != 0; in printShiftImmOperand()
818 unsigned Amt = ShiftOp & 0x1f; in printShiftImmOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 1082 unsigned ShiftOp; in PromoteIntRes_ADDSUBSHLSAT() local
1087 ShiftOp = ISD::SRA; in PromoteIntRes_ADDSUBSHLSAT()
1090 ShiftOp = ISD::SRL; in PromoteIntRes_ADDSUBSHLSAT()
1108 return matcher.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount); in PromoteIntRes_ADDSUBSHLSAT()
1153 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX() local
1154 return DAG.getNode(ShiftOp, dl, PromotedType, Result, in PromoteIntRes_MULFIX()
4747 SDValue ShiftOp = N->getOperand(1); in ExpandIntRes_Shift() local
4749 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
4750 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
4752 SDValue Ops[] = { LHSL, LHSH, ShiftOp }; in ExpandIntRes_Shift()
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| H A D | DAGCombiner.cpp | 2595 SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1); in foldAddSubOfSignBit() local
2597 ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2601 SDValue Not = ShiftOp.getOperand(0); in foldAddSubOfSignBit()
2606 EVT VT = ShiftOp.getValueType(); in foldAddSubOfSignBit()
2607 SDValue ShAmt = ShiftOp.getOperand(1); in foldAddSubOfSignBit()
6860 static SDValue foldLogicOfShifts(SDNode *N, SDValue LogicOp, SDValue ShiftOp, in foldLogicOfShifts() argument
6866 if (!LogicOp.hasOneUse() || !ShiftOp.hasOneUse()) in foldLogicOfShifts()
6870 unsigned ShiftOpcode = ShiftOp.getOpcode(); in foldLogicOfShifts()
6880 SDValue X1 = ShiftOp.getOperand(0); in foldLogicOfShifts()
6881 SDValue Y = ShiftOp.getOperand(1); in foldLogicOfShifts()
[all …]
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| H A D | SelectionDAGBuilder.cpp | 3267 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT); in visitBitTestCase() local
3276 ShiftOp, DAG.getConstant(llvm::countr_zero(B.Mask), dl, VT), in visitBitTestCase()
3282 ShiftOp, DAG.getConstant(llvm::countr_one(B.Mask), dl, VT), ISD::SETNE); in visitBitTestCase()
3286 DAG.getConstant(1, dl, VT), ShiftOp); in visitBitTestCase()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 2032 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA; in expandSelectBoolean() local
2033 Result = CurDAG->getNode(ShiftOp, DL, MVT::i32, Result, in expandSelectBoolean()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 2191 Instruction::BinaryOps ShiftOp = in foldBinOpOfDisplacedShifts() local
2193 if (ShiftOp != Op1Inst->getOpcode()) in foldBinOpOfDisplacedShifts()
2197 if (I.getOpcode() == Instruction::Add && ShiftOp != Instruction::Shl) in foldBinOpOfDisplacedShifts()
2201 I.getOpcode(), ShiftedC1, Builder.CreateBinOp(ShiftOp, ShiftedC2, AddC)); in foldBinOpOfDisplacedShifts()
2202 return BinaryOperator::Create(ShiftOp, NewC, ShAmt); in foldBinOpOfDisplacedShifts()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 11769 auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(1)); in calculateSrcByte() local
11770 if (!ShiftOp) in calculateSrcByte()
11773 uint64_t BitShift = ShiftOp->getZExtValue(); in calculateSrcByte()
11863 auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(2)); in calculateByteProvider() local
11864 if (!ShiftOp || Op.getValueType().isVector()) in calculateByteProvider()
11871 uint64_t BitShift = ShiftOp->getAPIntValue().urem(BitsProvided); in calculateByteProvider()
11890 auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(1)); in calculateByteProvider() local
11891 if (!ShiftOp) in calculateByteProvider()
11894 uint64_t BitShift = ShiftOp->getZExtValue(); in calculateByteProvider()
11918 auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(1)); in calculateByteProvider() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 3335 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL; in emitINSERT_DF_VIDX() local
3380 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1) in emitINSERT_DF_VIDX()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 2697 auto ShiftOp = [&](const APInt &Lhs, const APInt &Rhs) { in isNonZeroShift() local
2732 if (!ShiftOp(KnownVal.One, MaxShift).isZero()) in isNonZeroShift()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 8284 unsigned ShiftOp = IsSigned ? TargetOpcode::G_ASHR : TargetOpcode::G_LSHR; in lowerSMULH_UMULH() local
8287 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); in lowerSMULH_UMULH()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 246 for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) { in X86TargetLowering()
250 setOperationAction(ShiftOp , MVT::i8 , Custom); in X86TargetLowering()
251 setOperationAction(ShiftOp , MVT::i16 , Custom); in X86TargetLowering()
252 setOperationAction(ShiftOp , MVT::i32 , ShiftDoubleAction); in X86TargetLowering()
254 setOperationAction(ShiftOp , MVT::i64 , ShiftDoubleAction); in X86TargetLowering()
50881 SDValue ShiftOp = Shift.getOperand(0); in foldXorTruncShiftIntoCmp() local
50882 EVT ShiftOpTy = ShiftOp.getValueType(); in foldXorTruncShiftIntoCmp()
50886 SDValue Cond = DAG.getSetCC(DL, SetCCResultType, ShiftOp, in foldXorTruncShiftIntoCmp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 23055 SDValue ShiftOp = Index.getOperand(1); in foldIndexIntoBase() local
23057 if (auto Shift = DAG.getSplatValue(ShiftOp)) in foldIndexIntoBase()
23063 Add.getOperand(0), ShiftOp); in foldIndexIntoBase()
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