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Searched refs:ShiftAmount (Results 1 – 25 of 36) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInsertSingleUseVDST.cpp79 unsigned ShiftAmount = 4; in encodeImm() local
81 Imm |= SkipRegions[i - 1] << ShiftAmount; in encodeImm()
82 ShiftAmount += 3; in encodeImm()
83 Imm |= SingleUseRegions[i - 1] << ShiftAmount; in encodeImm()
84 ShiftAmount += 3; in encodeImm()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp285 uint64_t ShiftAmount = N->getConstantOperandVal(1); in LowerShifts() local
286 if (ShiftAmount == 16) { in LowerShifts()
302 SDValue Cnt = DAG.getTargetConstant(ShiftAmount, dl, MVT::i8); in LowerShifts()
353 uint64_t ShiftAmount = N->getConstantOperandVal(1); in LowerShifts() local
362 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
366 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
380 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) { in LowerShifts()
385 ShiftAmount -= 4; in LowerShifts()
386 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount && in LowerShifts()
387 ShiftAmount < 7) { in LowerShifts()
[all …]
H A DAVRShiftExpand.cpp94 Value *ShiftAmount = Builder.CreateTrunc(BI->getOperand(1), Int8Ty); in expand() local
98 Value *Cmp1 = Builder.CreateICmpEQ(ShiftAmount, Int8Zero); in expand()
105 ShiftAmountPHI->addIncoming(ShiftAmount, BB); in expand()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVBaseInfo.h261 for (unsigned ShiftAmount = 0; ShiftAmount < 32; ShiftAmount += 8) { in getSPIRVStringOperand() local
262 char c = (Imm >> ShiftAmount) & 0xff; in getSPIRVStringOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp109 int ShiftAmount = 0; in generateInstSeqImpl() local
114 ShiftAmount = llvm::countr_zero((uint64_t)Val); in generateInstSeqImpl()
115 Val >>= ShiftAmount; in generateInstSeqImpl()
120 if (ShiftAmount > 12 && !isInt<12>(Val)) { in generateInstSeqImpl()
124 ShiftAmount -= 12; in generateInstSeqImpl()
130 ShiftAmount -= 12; in generateInstSeqImpl()
149 if (ShiftAmount) { in generateInstSeqImpl()
151 Res.emplace_back(Opc, ShiftAmount); in generateInstSeqImpl()
/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DDivisionByConstantInfo.h24 unsigned ShiftAmount; ///< shift amount member
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYFrameLowering.cpp177 unsigned ShiftAmount = Log2(MaxAlignment); in emitPrologue() local
184 .addImm(ShiftAmount); in emitPrologue()
187 .addImm(ShiftAmount); in emitPrologue()
194 .addImm(ShiftAmount); in emitPrologue()
197 .addImm(ShiftAmount); in emitPrologue()
/freebsd/contrib/llvm-project/clang/lib/AST/Interp/
H A DIntegralAP.h262 unsigned ShiftAmount = B.V.getZExtValue(); in shiftRight() local
264 *R = IntegralAP(A.V.ashr(ShiftAmount)); in shiftRight()
266 *R = IntegralAP(A.V.lshr(ShiftAmount)); in shiftRight()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp350 uint32_t ShiftAmount = Log2_32(LMUL); in lowerVSPILL() local
351 if (ShiftAmount != 0) in lowerVSPILL()
354 .addImm(ShiftAmount); in lowerVSPILL()
427 uint32_t ShiftAmount = Log2_32(LMUL); in lowerVRELOAD() local
428 if (ShiftAmount != 0) in lowerVRELOAD()
431 .addImm(ShiftAmount); in lowerVRELOAD()
H A DRISCVInstrInfo.cpp3664 uint32_t ShiftAmount = Log2_32(Amount); in mulImm()
3665 if (ShiftAmount == 0) in mulImm()
3669 .addImm(ShiftAmount) in mulImm()
3677 uint32_t ShiftAmount; in mulImm()
3680 ShiftAmount = Log2_64(Amount / 9); in mulImm()
3683 ShiftAmount = Log2_64(Amount / 5); in mulImm()
3686 ShiftAmount = Log2_64(Amount / 3); in mulImm()
3690 if (ShiftAmount) in mulImm()
3693 .addImm(ShiftAmount) in mulImm()
3701 uint32_t ShiftAmount in mulImm()
3657 uint32_t ShiftAmount = Log2_32(Amount); mulImm() local
3670 uint32_t ShiftAmount; mulImm() local
3694 uint32_t ShiftAmount = Log2_32(Amount - 1); mulImm() local
3705 uint32_t ShiftAmount = Log2_32(Amount + 1); mulImm() local
3724 for (uint32_t ShiftAmount = 0; Amount >> ShiftAmount; ShiftAmount++) { mulImm() local
[all...]
H A DRISCVFrameLowering.cpp732 unsigned ShiftAmount = Log2(MaxAlignment); in emitPrologue() local
737 .addImm(ShiftAmount) in emitPrologue()
741 .addImm(ShiftAmount) in emitPrologue()
/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DDivisionByConstantInfo.cpp63 Retval.ShiftAmount = P - D.getBitWidth(); // resulting shift in get()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.h46 unsigned ShiftAmount) const;
H A DMipsTargetStreamer.h144 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
H A DMipsSEISelDAGToDAG.cpp283 unsigned ShiftAmount = 0) const { in selectAddrFrameIndexOffset() argument
286 if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) { in selectAddrFrameIndexOffset()
297 const Align Alignment(1ULL << ShiftAmount); in selectAddrFrameIndexOffset()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp274 int16_t ShiftAmount, SMLoc IDLoc, in emitDSLL() argument
276 if (ShiftAmount >= 32) { in emitDSLL()
277 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
281 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI); in emitDSLL()
H A DMipsMCCodeEmitter.h185 template <unsigned ShiftAmount = 0>
H A DMipsMCCodeEmitter.cpp742 template <unsigned ShiftAmount> in getMachineOpValue()
753 OffBits >>= ShiftAmount; in getMemEncoding()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp969 uint64_t ShiftAmount = N->getConstantOperandVal(1); in LowerShifts() local
974 if (ShiftAmount >= 8) { in LowerShifts()
994 ShiftAmount -= 8; in LowerShifts()
997 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
1001 ShiftAmount -= 1; in LowerShifts()
1004 while (ShiftAmount--) in LowerShifts()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp1742 static bool shiftAmountKnownInRange(Register ShiftAmount, in shiftAmountKnownInRange() argument
1744 LLT Ty = MRI.getType(ShiftAmount); in shiftAmountKnownInRange()
1751 getIConstantVRegValWithLookThrough(ShiftAmount, MRI); in shiftAmountKnownInRange()
1757 GBuildVector *BV = getOpcodeDef<GBuildVector>(ShiftAmount, MRI); in shiftAmountKnownInRange()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp437 unsigned ShiftAmount; member
618 return ShiftedImm.ShiftAmount; in getShiftedImmShift()
976 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImm()
2266 unsigned ShiftAmount = 0, in CreateReg() argument
2274 Op->Reg.ShiftExtend.Amount = ShiftAmount; in CreateReg()
2285 unsigned ShiftAmount = 0, in CreateVectorReg() argument
2291 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount, in CreateVectorReg()
2371 unsigned ShiftAmount, in CreateShiftedImm() argument
2376 Op->ShiftedImm.ShiftAmount = ShiftAmount; in CreateShiftedImm()
3403 int64_t ShiftAmount = getTok().getIntVal(); in tryParseImmWithOptionalShift() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DValueTracking.cpp7210 static bool shiftAmountKnownInRange(const Value *ShiftAmount) { in shiftAmountKnownInRange() argument
7211 auto *C = dyn_cast<Constant>(ShiftAmount); in shiftAmountKnownInRange()
9375 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
9377 ShiftAmount = C->countr_zero(); in setLimitsForBinOp()
9381 Upper = C->ashr(ShiftAmount) + 1; in setLimitsForBinOp()
9384 Lower = C->ashr(ShiftAmount); in setLimitsForBinOp()
9396 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
9398 ShiftAmount = C->countr_zero(); in setLimitsForBinOp()
9399 Lower = C->lshr(ShiftAmount); in setLimitsForBinOp()
9413 unsigned ShiftAmount = C->countl_one() - 1; in setLimitsForBinOp() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp1270 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); in ExpandSIGN_EXTEND_VECTOR_INREG() local
1272 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
1273 ShiftAmount); in ExpandSIGN_EXTEND_VECTOR_INREG()
H A DTargetLowering.cpp2322 unsigned ShiftAmount = NLZ > NTZ ? NLZ - NTZ : NTZ - NLZ; in SimplifyDemandedBits() local
2323 SDValue ShAmt = TLO.DAG.getShiftAmountConstant(ShiftAmount, VT, dl); in SimplifyDemandedBits()
6334 magics.ShiftAmount = 0; in BuildSDIV()
6346 Shifts.push_back(DAG.getConstant(magics.ShiftAmount, dl, ShSVT)); in BuildSDIV()
7625 unsigned ShiftAmount = OuterBitSize - InnerBitSize; in expandMUL_LOHI() local
7626 SDValue Shift = DAG.getShiftAmountConstant(ShiftAmount, VT, dl); in expandMUL_LOHI()
9664 SDValue ShiftAmount = DAG.getShiftAmountConstant( in scalarizeVectorLoad() local
9666 SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount); in scalarizeVectorLoad()
9748 SDValue ShiftAmount = in scalarizeVectorStore() local
9751 DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount); in scalarizeVectorStore()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp2008 uint64_t ShiftAmount = V.getConstantOperandVal(1); in factorOutPowerOf2() local
2009 if (ShiftAmount == Power) in factorOutPowerOf2()
2011 Ops[1] = CurDAG->getConstant(ShiftAmount - Power, in factorOutPowerOf2()

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