| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 98 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
99 return ShOp | (Imm << 3); in getSORegOpc()
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| H A D | ARMMCCodeEmitter.cpp | 1287 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue() local
1288 unsigned SBits = getShiftOp(ShOp); in getLdStSORegOpValue()
1325 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue() local
1327 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] in getAddrMode2OffsetOpValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrNEON.td | 2660 ValueType Ty, SDNode ShOp>
2665 (Ty (ShOp (Ty DPR:$Vn),
2672 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2677 (Ty (ShOp (Ty DPR:$Vn),
2708 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2713 (ResTy (ShOp (ResTy QPR:$Vn),
2721 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2726 (ResTy (ShOp (ResTy QPR:$Vn),
2874 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2881 (Ty (ShOp (Ty DPR:$src1),
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 2573 CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val, in CreateShiftExtend() argument
2576 Op->ShiftExtend.Type = ShOp; in CreateShiftExtend()
3653 AArch64_AM::ShiftExtendType ShOp = in tryParseOptionalShiftExtend() local
3670 if (ShOp == AArch64_AM::InvalidShiftExtend) in tryParseOptionalShiftExtend()
3679 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR || in tryParseOptionalShiftExtend()
3680 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
3681 ShOp == AArch64_AM::MSL) { in tryParseOptionalShiftExtend()
3689 AArch64Operand::CreateShiftExtend(ShOp, 0, false, S, E, getContext())); in tryParseOptionalShiftExtend()
3710 ShOp, MCE->getValue(), true, S, E, getContext())); in tryParseOptionalShiftExtend()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 2165 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand() local
2168 ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
2171 ShOp = ARM_AM::lsr; in DecodeSORegMemOperand()
2174 ShOp = ARM_AM::asr; in DecodeSORegMemOperand()
2177 ShOp = ARM_AM::ror; in DecodeSORegMemOperand()
2181 if (ShOp == ARM_AM::ror && imm == 0) in DecodeSORegMemOperand()
2182 ShOp = ARM_AM::rrx; in DecodeSORegMemOperand()
2190 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); in DecodeSORegMemOperand()
2192 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); in DecodeSORegMemOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 1515 Value *ShOp; in foldICmpTruncConstant() local
1519 match(X, m_Shr(m_Value(ShOp), m_APInt(ShAmtC))) && in foldICmpTruncConstant()
1521 return TrueIfSigned ? new ICmpInst(ICmpInst::ICMP_SLT, ShOp, in foldICmpTruncConstant()
1523 : new ICmpInst(ICmpInst::ICMP_SGT, ShOp, in foldICmpTruncConstant()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6290 SDValue ShOp = N0.getOperand(1); in hoistLogicOpWithSameOpcodeHands() local
6291 if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) in hoistLogicOpWithSameOpcodeHands()
6292 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); in hoistLogicOpWithSameOpcodeHands()
6295 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) { in hoistLogicOpWithSameOpcodeHands()
6298 return DAG.getVectorShuffle(VT, DL, Logic, ShOp, SVN0->getMask()); in hoistLogicOpWithSameOpcodeHands()
6303 ShOp = N0.getOperand(0); in hoistLogicOpWithSameOpcodeHands()
6304 if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) in hoistLogicOpWithSameOpcodeHands()
6305 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); in hoistLogicOpWithSameOpcodeHands()
6308 if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) { in hoistLogicOpWithSameOpcodeHands()
6311 return DAG.getVectorShuffle(VT, DL, ShOp, Logic, SVN0->getMask()); in hoistLogicOpWithSameOpcodeHands()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 1411 class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp,
1413 : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)),
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