| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchFloat32InstrInfo.td | 181 /// Setcc
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| H A D | LoongArchFloat64InstrInfo.td | 164 /// Setcc
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| H A D | LoongArchInstrInfo.td | 1391 /// Setcc
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 563 bool tryVPTESTM(SDNode *Root, SDValue Setcc, SDValue Mask);
4859 bool X86DAGToDAGISel::tryVPTESTM(SDNode *Root, SDValue Setcc, in tryVPTESTM() argument
4862 assert(Setcc.getSimpleValueType().getVectorElementType() == MVT::i1 && in tryVPTESTM()
4866 ISD::CondCode CC = cast<CondCodeSDNode>(Setcc.getOperand(2))->get(); in tryVPTESTM()
4870 SDValue SetccOp0 = Setcc.getOperand(0); in tryVPTESTM()
4871 SDValue SetccOp1 = Setcc.getOperand(1); in tryVPTESTM()
4958 MVT ResVT = Setcc.getSimpleValueType(); in tryVPTESTM()
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| H A D | X86ScheduleBtVer2.td | 230 def : WriteRes<WriteSETCC, [JALU01]>; // Setcc.
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| H A D | X86SchedSandyBridge.td | 179 def : WriteRes<WriteSETCC, [SBPort05]>; // Setcc.
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| H A D | X86ScheduleBdVer2.td | 493 def : WriteRes<WriteSETCC, [PdEX01]>; // Setcc.
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| H A D | X86SchedBroadwell.td | 184 def : WriteRes<WriteSETCC, [BWPort06]>; // Setcc.
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| H A D | X86SchedSkylakeClient.td | 167 def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
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| H A D | X86SchedHaswell.td | 186 def : WriteRes<WriteSETCC, [HWPort06]>; // Setcc.
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| H A D | X86SchedSkylakeServer.td | 168 def : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc.
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| H A D | X86SchedIceLake.td | 175 def : WriteRes<WriteSETCC, [ICXPort06]>; // Setcc.
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| H A D | X86ISelLowering.cpp | 44487 SDValue Setcc = DAG.getSetCC(DL, SetccVT, Movmsk, CmpC, CondCode); in combinePredicateReduction() local
44488 SDValue Zext = DAG.getZExtOrTrunc(Setcc, DL, ExtractVT); in combinePredicateReduction()
53920 SDValue Setcc = DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, N0->getOperand(0), in combineSext() local
53923 DCI.CombineTo(N, Setcc); in combineSext()
53927 N0.getValueType(), Setcc); in combineSext()
54136 SDValue Setcc = DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, N0->getOperand(0), in combineZext() local
54139 DCI.CombineTo(N, Setcc); in combineZext()
54143 N0.getValueType(), Setcc); in combineZext()
54198 SDValue Setcc = DAG.getSetCC(DL, OpVT, LHS, RHS, CC); in truncateAVX512SetCCNoBWI() local
54199 return DAG.getNode(ISD::TRUNCATE, DL, VT, Setcc); in truncateAVX512SetCCNoBWI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 9005 SDValue Setcc = in lowerCttzElts()
9008 return DAG.getSelect(DL, XLenVT, Setcc, VL, Res);
13849 SDValue Setcc = DAG.getSetCC(SDLoc(N00), N0.getOperand(0).getValueType(), in performXORCombine()
13851 return DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N->getValueType(0), Setcc); in performXORCombine()
15724 SDValue Setcc = Cond.getOperand(0); in tryDemorganOfBooleanCondition()
15727 if (Setcc.getOpcode() != ISD::SETCC) in tryDemorganOfBooleanCondition()
15728 std::swap(Setcc, Xor); in tryDemorganOfBooleanCondition()
15730 if (Setcc.getOpcode() != ISD::SETCC || !Setcc.hasOneUse() || in tryDemorganOfBooleanCondition()
15749 EVT SetCCOpVT = Setcc in tryDemorganOfBooleanCondition()
9003 SDValue Setcc = lowerCttzElts() local
13846 SDValue Setcc = DAG.getSetCC(SDLoc(N00), N0.getOperand(0).getValueType(), performXORCombine() local
15721 SDValue Setcc = Cond.getOperand(0); tryDemorganOfBooleanCondition() local
[all...] |
| H A D | RISCVInstrInfoD.td | 396 /// Setcc
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| H A D | RISCVInstrInfoZfh.td | 352 /// Setcc
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| H A D | RISCVInstrInfoF.td | 603 /// Setcc
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| H A D | RISCVInstrInfo.td | 1373 /// Setcc
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 6829 SDValue Setcc = DAG.getSetCC(DL, CCVT, NewAnd, Zero, ISD::SETEQ); in combineShiftAnd1ToBitTest() local
6830 return DAG.getZExtOrTrunc(Setcc, DL, And->getValueType(0)); in combineShiftAnd1ToBitTest()
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