| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchFloat64InstrInfo.td | 166 /// Setcc
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| H A D | LoongArchFloat32InstrInfo.td | 187 /// Setcc
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| H A D | LoongArchInstrInfo.td | 1462 /// Setcc
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 607 bool tryVPTESTM(SDNode *Root, SDValue Setcc, SDValue Mask);
4927 bool X86DAGToDAGISel::tryVPTESTM(SDNode *Root, SDValue Setcc, in tryVPTESTM() argument
4930 assert(Setcc.getSimpleValueType().getVectorElementType() == MVT::i1 && in tryVPTESTM()
4934 ISD::CondCode CC = cast<CondCodeSDNode>(Setcc.getOperand(2))->get(); in tryVPTESTM()
4938 SDValue SetccOp0 = Setcc.getOperand(0); in tryVPTESTM()
4939 SDValue SetccOp1 = Setcc.getOperand(1); in tryVPTESTM()
5026 MVT ResVT = Setcc.getSimpleValueType(); in tryVPTESTM()
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| H A D | X86ScheduleBtVer2.td | 230 def : WriteRes<WriteSETCC, [JALU01]>; // Setcc.
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| H A D | X86SchedSandyBridge.td | 179 def : WriteRes<WriteSETCC, [SBPort05]>; // Setcc.
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| H A D | X86ScheduleBdVer2.td | 493 def : WriteRes<WriteSETCC, [PdEX01]>; // Setcc.
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| H A D | X86SchedSkylakeClient.td | 167 def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
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| H A D | X86SchedBroadwell.td | 184 def : WriteRes<WriteSETCC, [BWPort06]>; // Setcc.
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| H A D | X86SchedHaswell.td | 186 def : WriteRes<WriteSETCC, [HWPort06]>; // Setcc.
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| H A D | X86SchedSkylakeServer.td | 168 def : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc.
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| H A D | X86SchedIceLake.td | 175 def : WriteRes<WriteSETCC, [ICXPort06]>; // Setcc.
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| H A D | X86ISelLowering.cpp | 46316 SDValue Setcc = DAG.getSetCC(DL, SetccVT, Movmsk, CmpC, CondCode); in combinePredicateReduction() local
46317 SDValue Zext = DAG.getZExtOrTrunc(Setcc, DL, ExtractVT); in combinePredicateReduction()
55784 SDValue Setcc = DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, N0->getOperand(0), in combineSext() local
55787 DCI.CombineTo(N, Setcc); in combineSext()
55791 N0.getValueType(), Setcc); in combineSext()
56083 SDValue Setcc = DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, N0->getOperand(0), in combineZext() local
56086 DCI.CombineTo(N, Setcc); in combineZext()
56090 N0.getValueType(), Setcc); in combineZext()
56148 SDValue Setcc = DAG.getSetCC(DL, OpVT, LHS, RHS, CC); in truncateAVX512SetCCNoBWI() local
56149 return DAG.getNode(ISD::TRUNCATE, DL, VT, Setcc); in truncateAVX512SetCCNoBWI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 10522 SDValue Setcc = in lowerCttzElts() local
10525 return DAG.getSelect(DL, XLenVT, Setcc, VL, Res); in lowerCttzElts()
18229 SDValue Setcc = Cond.getOperand(0); in tryDemorganOfBooleanCondition() local
18232 if (Setcc.getOpcode() != ISD::SETCC) in tryDemorganOfBooleanCondition()
18233 std::swap(Setcc, Xor); in tryDemorganOfBooleanCondition()
18235 if (Setcc.getOpcode() != ISD::SETCC || !Setcc.hasOneUse() || in tryDemorganOfBooleanCondition()
18254 EVT SetCCOpVT = Setcc.getOperand(0).getValueType(); in tryDemorganOfBooleanCondition()
18258 ISD::CondCode CCVal = cast<CondCodeSDNode>(Setcc.getOperand(2))->get(); in tryDemorganOfBooleanCondition()
18261 Setcc = DAG.getSetCC(SDLoc(Setcc), VT, Setcc.getOperand(0), in tryDemorganOfBooleanCondition()
18262 Setcc.getOperand(1), CCVal); in tryDemorganOfBooleanCondition()
[all …]
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| H A D | RISCVInstrInfoZfh.td | 386 /// Setcc
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| H A D | RISCVInstrInfoD.td | 407 /// Setcc
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| H A D | RISCVInstrInfoF.td | 661 /// Setcc
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| H A D | RISCVInstrInfo.td | 1603 /// Setcc
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 7221 SDValue Setcc = DAG.getSetCC(DL, CCVT, NewAnd, Zero, ISD::SETEQ); in combineShiftAnd1ToBitTest() local
7222 return DAG.getZExtOrTrunc(Setcc, DL, And->getValueType(0)); in combineShiftAnd1ToBitTest()
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