| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrCMovSetCC.td | 1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
139 // SetCC instructions.
151 // SetZUCC and promoted SetCC instructions.
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| H A D | X86ISelLowering.cpp | 24011 SDValue SetCC = getSETCC(Cond, Overflow, DL, DAG); in LowerXALUO() local
24013 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), Value, SetCC); in LowerXALUO()
25943 SDValue SetCC; in LowerINTRINSIC_WO_CHAIN() local
25946 SetCC = getSETCC(X86::COND_E, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
25948 SetCC = DAG.getNode(ISD::AND, dl, MVT::i8, SetCC, SetNP); in LowerINTRINSIC_WO_CHAIN()
25952 SetCC = getSETCC(X86::COND_NE, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
25954 SetCC = DAG.getNode(ISD::OR, dl, MVT::i8, SetCC, SetP); in LowerINTRINSIC_WO_CHAIN()
25959 SetCC = getSETCC(X86::COND_A, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
25964 SetCC = getSETCC(X86::COND_AE, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
25969 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 1260 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSHL_PARTS() local
1261 LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi); in LowerSHL_PARTS()
1271 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE); in LowerSHL_PARTS()
1273 DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift); in LowerSHL_PARTS()
1279 dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift); in LowerSHL_PARTS()
1308 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE); in LowerSRL_PARTS() local
1311 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi); in LowerSRL_PARTS()
1314 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo); in LowerSRL_PARTS()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrP10.td | 1968 multiclass IntSetP10RevSetBool<SDNode SetCC, ValueType Ty, PatLeaf ZExtTy,
1971 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
1973 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
1975 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
1977 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
1979 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
1982 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETUGE)),
1984 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETGE)),
1986 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)),
1988 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETLE)),
[all …]
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| H A D | PPCInstrInfo.td | 3909 multiclass FSetCCPat<SDPatternOperator SetCC, ValueType Ty, I FCmp> {
3910 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
3912 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
3914 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
3916 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
3918 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)),
3920 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
3922 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)),
3925 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)),
3927 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)),
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 691 SDValue SetCC = N->getOperand(0); in performSELECTCombine() local
693 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
694 !SetCC.getOperand(0).getValueType().isInteger()) in performSELECTCombine()
718 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
721 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
722 SetCC.getOperand(1), in performSELECTCombine()
723 ISD::getSetCCInverse(CC, SetCC.getValueType())); in performSELECTCombine()
725 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); in performSELECTCombine()
748 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); in performSELECTCombine()
755 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
[all …]
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| H A D | MipsSEISelLowering.cpp | 984 SDValue SetCC = N->getOperand(0); in performVSELECTCombine() local
986 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) in performVSELECTCombine()
990 SetCC.getOperand(0), SetCC.getOperand(1), in performVSELECTCombine()
991 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine()
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| H A D | MipsInstrInfo.td | 1520 // SetCC
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VVPInstrInfo.td | 104 // SetCC (lhs, rhs, cc, mask, vl)
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 19003 SDValue SetCC = N->getOperand(0); in performANDSETCCCombine() local
19015 if (SetCC.getOpcode() == ISD::SETCC && in performANDSETCCCombine()
19016 SetCC.getOperand(0).getValueType() == MVT::f32) { in performANDSETCCCombine()
21558 const SDValue SetCC = N->getOperand(0); in performSignExtendSetCCCombine() local
21560 const SDValue CCOp0 = SetCC.getOperand(0); in performSignExtendSetCCCombine()
21561 const SDValue CCOp1 = SetCC.getOperand(1); in performSignExtendSetCCCombine()
21567 cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get(); in performSignExtendSetCCCombine()
21572 if (isCheapToExtend(SetCC.getOperand(0)) && in performSignExtendSetCCCombine()
21573 isCheapToExtend(SetCC.getOperand(1))) { in performSignExtendSetCCCombine()
21580 SDLoc(SetCC), N->getValueType(0), Ext1, Ext2, in performSignExtendSetCCCombine()
[all …]
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| H A D | AArch64InstrInfo.td | 5632 // The following SetCC patterns are used for GlobalISel only
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 895 SDValue SetCC = in Expand() local
898 Results.push_back(DAG.getSelect(SDLoc(Node), Node->getValueType(0), SetCC, in Expand()
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| H A D | DAGCombiner.cpp | 9474 SDValue SetCC = in visitXOR() local
9477 CombineTo(N, SetCC); in visitXOR()
9478 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), SetCC.getValue(1)); in visitXOR()
13014 for (SDNode *SetCC : SetCCs) { in ExtendSetCCUses()
13018 SDValue SOp = SetCC->getOperand(j); in ExtendSetCCUses()
13025 Ops.push_back(SetCC->getOperand(2)); in ExtendSetCCUses()
13026 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops)); in ExtendSetCCUses()
13229 SDValue SetCC = VSel.getOperand(0); in matchVSelectOpSizesWithSetCC() local
13230 EVT SetCCVT = getSetCCResultType(SetCC.getOperand(0).getValueType()); in matchVSelectOpSizesWithSetCC()
13247 return DAG.getNode(ISD::VSELECT, DL, VT, SetCC, CastA, CastB); in matchVSelectOpSizesWithSetCC()
[all …]
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| H A D | LegalizeIntegerTypes.cpp | 1359 SDValue SetCC; in PromoteIntRes_SETCC() local
1364 SetCC = DAG.getNode(N->getOpcode(), dl, VTs, Opers, N->getFlags()); in PromoteIntRes_SETCC()
1367 ReplaceValueWith(SDValue(N, 1), SetCC.getValue(1)); in PromoteIntRes_SETCC()
1369 SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0), in PromoteIntRes_SETCC()
1373 return DAG.getSExtOrTrunc(SetCC, dl, NVT); in PromoteIntRes_SETCC()
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| H A D | TargetLowering.cpp | 10895 SDValue SetCC; in expandUADDSUBO() local
10902 SetCC = in expandUADDSUBO()
10907 SetCC = in expandUADDSUBO()
10912 SetCC = DAG.getSetCC(dl, SetCCType, Result, LHS, CC); in expandUADDSUBO()
10914 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); in expandUADDSUBO()
10935 SDValue SetCC = DAG.getSetCC(dl, OType, Result, Sat, ISD::SETNE); in expandSADDSUBO() local
10936 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); in expandSADDSUBO()
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| H A D | SelectionDAGBuilder.cpp | 7950 SDValue SetCC = DAG.getSetCC(sdl, CCVT, VectorInduction, in visitIntrinsicCall() local
7952 setValue(&I, SetCC); in visitIntrinsicCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 2179 SDValue SetCC = in LowerSETCC() local
2183 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in LowerSETCC()
2184 return SetCC; in LowerSETCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 4335 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); in lowerXALUO() local
4337 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerXALUO()
4339 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerXALUO()
4433 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); in lowerUADDSUBO_CARRY() local
4435 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerUADDSUBO_CARRY()
4437 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerUADDSUBO_CARRY()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 6040 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS, in lowerICMPIntrinsic() local
6043 return SetCC; in lowerICMPIntrinsic()
6044 return DAG.getZExtOrTrunc(SetCC, DL, VT); in lowerICMPIntrinsic()
6069 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, in lowerFCMPIntrinsic() local
6072 return SetCC; in lowerFCMPIntrinsic()
6073 return DAG.getZExtOrTrunc(SetCC, SL, VT); in lowerFCMPIntrinsic()
6551 SDNode *SetCC = nullptr; in LowerBRCOND() local
6555 SetCC = Intr; in LowerBRCOND()
6556 Intr = SetCC->getOperand(0).getNode(); in LowerBRCOND()
6574 assert(!SetCC || in LowerBRCOND()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 3129 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, ResTy, in WidenHvxSetCC() local
3134 {SetCC, getZero(dl, MVT::i32, DAG)}); in WidenHvxSetCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2383 // Changes the condition code and swaps operands if necessary, so the SetCC
5551 SDValue SetCC = in lowerVPCttzElements()
5553 Res = DAG.getSelect(DL, XLenVT, SetCC, EVL, Res); in lowerVPCttzElements()
6969 SDValue SetCC = DAG.getSetCC( in LowerOperation()
6971 return DAG.getLogicalNOT(DL, SetCC, VT); in LowerOperation()
9778 SDValue SetCC = DAG.getSetCC(DL, XLenVT, Vec, Zero, CC); in lowerVectorMaskVecReduction()
9779 SetCC = DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), SetCC); in lowerVectorMaskVecReduction()
9782 return SetCC; in lowerVectorMaskVecReduction()
9790 return DAG.getNode(BaseOpc, DL, Op.getValueType(), SetCC, O in lowerVectorMaskVecReduction()
5550 SDValue SetCC = lowerVPCttzElements() local
6967 SDValue SetCC = DAG.getSetCC( LowerOperation() local
9776 SDValue SetCC = DAG.getSetCC(DL, XLenVT, Vec, Zero, CC); lowerVectorMaskVecReduction() local
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13215 SDValue SetCC; in PerformSELECTCombine() local
13224 SetCC = N->getOperand(0); in PerformSELECTCombine()
13225 LHS = SetCC->getOperand(0); in PerformSELECTCombine()
13226 RHS = SetCC->getOperand(1); in PerformSELECTCombine()
13227 CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); in PerformSELECTCombine()
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