| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrCMovSetCC.td | 1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===//
139 // SetCC instructions.
151 // SetZUCC and promoted SetCC instructions.
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| H A D | X86ISelLowering.cpp | 24786 SDValue SetCC = getSETCC(Cond, Overflow, DL, DAG); in LowerXALUO() local
24788 return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), Value, SetCC); in LowerXALUO()
26814 SDValue SetCC; in LowerINTRINSIC_WO_CHAIN() local
26817 SetCC = getSETCC(X86::COND_E, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
26822 SetCC = DAG.getNode(ISD::AND, dl, MVT::i8, SetCC, SetNP); in LowerINTRINSIC_WO_CHAIN()
26826 SetCC = getSETCC(X86::COND_NE, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
26831 SetCC = DAG.getNode(ISD::OR, dl, MVT::i8, SetCC, SetP); in LowerINTRINSIC_WO_CHAIN()
26836 SetCC = getSETCC(X86::COND_A, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
26841 SetCC = getSETCC(X86::COND_AE, Comi, dl, DAG); in LowerINTRINSIC_WO_CHAIN()
26846 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 1214 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ); in LowerSHL_PARTS() local
1215 LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi); in LowerSHL_PARTS()
1225 SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE); in LowerSHL_PARTS()
1227 DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift); in LowerSHL_PARTS()
1233 dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift); in LowerSHL_PARTS()
1262 SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE); in LowerSRL_PARTS() local
1265 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi); in LowerSRL_PARTS()
1268 Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo); in LowerSRL_PARTS()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrP10.td | 1974 multiclass IntSetP10RevSetBool<SDNode SetCC, ValueType Ty, PatLeaf ZExtTy,
1977 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
1979 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
1981 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
1983 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
1985 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
1988 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETUGE)),
1990 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETGE)),
1992 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)),
1994 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, SExtTy:$imm, SETLE)),
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| H A D | PPCInstrInfo.td | 3949 multiclass FSetCCPat<SDPatternOperator SetCC, ValueType Ty, I FCmp> {
3950 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
3952 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)),
3954 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
3956 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)),
3958 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)),
3960 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)),
3962 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)),
3965 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)),
3967 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)),
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 700 SDValue SetCC = N->getOperand(0); in performSELECTCombine() local
702 if ((SetCC.getOpcode() != ISD::SETCC) || in performSELECTCombine()
703 !SetCC.getOperand(0).getValueType().isInteger()) in performSELECTCombine()
727 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
730 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), in performSELECTCombine()
731 SetCC.getOperand(1), in performSELECTCombine()
732 ISD::getSetCCInverse(CC, SetCC.getValueType())); in performSELECTCombine()
734 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); in performSELECTCombine()
757 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); in performSELECTCombine()
764 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine()
[all …]
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| H A D | MipsSEISelLowering.cpp | 1023 SDValue SetCC = N->getOperand(0); in performVSELECTCombine() local
1025 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) in performVSELECTCombine()
1029 SetCC.getOperand(0), SetCC.getOperand(1), in performVSELECTCombine()
1030 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine()
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| H A D | MipsInstrInfo.td | 1532 // SetCC
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VVPInstrInfo.td | 104 // SetCC (lhs, rhs, cc, mask, vl)
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 19646 SDValue SetCC = N->getOperand(0); in performANDSETCCCombine() local
19658 if (SetCC.getOpcode() == ISD::SETCC && in performANDSETCCCombine()
19659 SetCC.getOperand(0).getValueType() == MVT::f32) { in performANDSETCCCombine()
22425 const SDValue SetCC = N->getOperand(0); in performSignExtendSetCCCombine() local
22427 const SDValue CCOp0 = SetCC.getOperand(0); in performSignExtendSetCCCombine()
22428 const SDValue CCOp1 = SetCC.getOperand(1); in performSignExtendSetCCCombine()
22434 cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get(); in performSignExtendSetCCCombine()
22439 if (isCheapToExtend(SetCC.getOperand(0)) && in performSignExtendSetCCCombine()
22440 isCheapToExtend(SetCC.getOperand(1))) { in performSignExtendSetCCCombine()
22447 SDLoc(SetCC), N->getValueType(0), Ext1, Ext2, in performSignExtendSetCCCombine()
[all …]
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| H A D | AArch64InstrInfo.td | 6091 // The following SetCC patterns are used for GlobalISel only
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 2181 SDValue SetCC = in LowerSETCC() local
2185 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in LowerSETCC()
2186 return SetCC; in LowerSETCC()
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| H A D | M68kInstrInfo.td | 159 // M68k SetCC. Operand 0 is condition code, and operand 1 is the CCR
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 1004 SDValue SetCC = in Expand() local
1007 Results.push_back(DAG.getSelect(SDLoc(Node), Node->getValueType(0), SetCC, in Expand()
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| H A D | DAGCombiner.cpp | 9928 SDValue SetCC = in visitXOR() local
9931 CombineTo(N, SetCC); in visitXOR()
9932 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), SetCC.getValue(1)); in visitXOR()
13874 for (SDNode *SetCC : SetCCs) { in ExtendSetCCUses()
13878 SDValue SOp = SetCC->getOperand(j); in ExtendSetCCUses()
13885 Ops.push_back(SetCC->getOperand(2)); in ExtendSetCCUses()
13886 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops)); in ExtendSetCCUses()
14089 SDValue SetCC = VSel.getOperand(0); in matchVSelectOpSizesWithSetCC() local
14090 EVT SetCCVT = getSetCCResultType(SetCC.getOperand(0).getValueType()); in matchVSelectOpSizesWithSetCC()
14107 return DAG.getNode(ISD::VSELECT, DL, VT, SetCC, CastA, CastB); in matchVSelectOpSizesWithSetCC()
[all …]
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| H A D | LegalizeIntegerTypes.cpp | 1404 SDValue SetCC; in PromoteIntRes_SETCC() local
1409 SetCC = DAG.getNode(N->getOpcode(), dl, VTs, Opers, N->getFlags()); in PromoteIntRes_SETCC()
1412 ReplaceValueWith(SDValue(N, 1), SetCC.getValue(1)); in PromoteIntRes_SETCC()
1414 SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0), in PromoteIntRes_SETCC()
1418 return DAG.getSExtOrTrunc(SetCC, dl, NVT); in PromoteIntRes_SETCC()
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| H A D | TargetLowering.cpp | 11397 SDValue SetCC; in expandUADDSUBO() local
11404 SetCC = in expandUADDSUBO()
11409 SetCC = in expandUADDSUBO()
11414 SetCC = DAG.getSetCC(dl, SetCCType, Result, LHS, CC); in expandUADDSUBO()
11416 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); in expandUADDSUBO()
11437 SDValue SetCC = DAG.getSetCC(dl, OType, Result, Sat, ISD::SETNE); in expandSADDSUBO() local
11438 Overflow = DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType); in expandSADDSUBO()
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| H A D | SelectionDAGBuilder.cpp | 8053 SDValue SetCC = DAG.getSetCC(sdl, CCVT, VectorInduction, in visitIntrinsicCall() local
8055 setValue(&I, SetCC); in visitIntrinsicCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 4806 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); in lowerXALUO() local
4808 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerXALUO()
4810 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerXALUO()
4908 SDValue SetCC = emitSETCC(DAG, DL, Result.getValue(1), CCValid, CCMask); in lowerUADDSUBO_CARRY() local
4910 SetCC = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in lowerUADDSUBO_CARRY()
4912 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC); in lowerUADDSUBO_CARRY()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 6384 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS, in lowerICMPIntrinsic() local
6387 return SetCC; in lowerICMPIntrinsic()
6388 return DAG.getZExtOrTrunc(SetCC, DL, VT); in lowerICMPIntrinsic()
6413 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, Src1, in lowerFCMPIntrinsic() local
6416 return SetCC; in lowerFCMPIntrinsic()
6417 return DAG.getZExtOrTrunc(SetCC, SL, VT); in lowerFCMPIntrinsic()
6914 SDNode *SetCC = nullptr; in LowerBRCOND() local
6918 SetCC = Intr; in LowerBRCOND()
6919 Intr = SetCC->getOperand(0).getNode(); in LowerBRCOND()
6937 assert(!SetCC || in LowerBRCOND()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 3166 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, ResTy, in WidenHvxSetCC() local
3171 {SetCC, getZero(dl, MVT::i32, DAG)}); in WidenHvxSetCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 6505 SDValue SetCC = in lowerVPCttzElements() local
6507 Res = DAG.getSelect(DL, XLenVT, SetCC, EVL, Res); in lowerVPCttzElements()
8085 SDValue SetCC = DAG.getSetCC( in LowerOperation() local
8087 return DAG.getLogicalNOT(DL, SetCC, VT); in LowerOperation()
11168 SDValue SetCC = DAG.getSetCC(DL, XLenVT, Vec, Zero, CC); in lowerVectorMaskVecReduction() local
11169 SetCC = DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), SetCC); in lowerVectorMaskVecReduction()
11172 return SetCC; in lowerVectorMaskVecReduction()
11181 return DAG.getNode(BaseOpc, DL, Op.getValueType(), SetCC, Op.getOperand(0)); in lowerVectorMaskVecReduction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13282 SDValue SetCC; in PerformSELECTCombine() local
13291 SetCC = N->getOperand(0); in PerformSELECTCombine()
13292 LHS = SetCC->getOperand(0); in PerformSELECTCombine()
13293 RHS = SetCC->getOperand(1); in PerformSELECTCombine()
13294 CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); in PerformSELECTCombine()
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