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Searched refs:SchedReads (Results 1 – 4 of 4) sorted by relevance

/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenSchedule.h436 std::vector<CodeGenSchedRW> SchedReads; variable
522 assert(Idx < SchedReads.size() && "bad SchedRead index"); in getSchedRead()
523 assert(SchedReads[Idx].isValid() && "invalid SchedRead"); in getSchedRead()
524 return SchedReads[Idx]; in getSchedRead()
H A DCodeGenSchedule.cpp612 SchedReads.resize(1); in collectSchedRW()
688 SchedReads.emplace_back(SchedReads.size(), SRDef); in collectSchedRW()
713 } for (unsigned RIdx = 0, REnd = SchedReads.size(); RIdx != REnd; in collectSchedRW()
716 SchedReads[RIdx].dump(); in collectSchedRW()
743 const std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites; in getSchedRWIdx()
840 std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites; in findRWForSequence()
860 std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites; in findOrInsertRW()
935 dbgs() << " " << SchedReads[Read].Name; in collectSchedClasses()
953 dbgs() << " " << SchedReads[RIdx].Name; in collectSchedClasses()
991 Name += SchedReads[Idx].Name; in createSchedClassName()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleR52.td45 // Cortex-R52 specific SchedReads
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoV.td100 // `reads` SchedReads that are listed for each explicit use operand.