| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineVectorOps.cpp | 647 Value *ScalarOp = IEI->getOperand(1); in collectSingleShuffleElements() local
654 if (isa<PoisonValue>(ScalarOp)) { // inserting poison into vector. in collectSingleShuffleElements()
662 } else if (ExtractElementInst *EI = dyn_cast<ExtractElementInst>(ScalarOp)){ in collectSingleShuffleElements()
801 Value *ScalarOp = IEI->getOperand(1); in collectShuffleElements() local
804 if (ExtractElementInst *EI = dyn_cast<ExtractElementInst>(ScalarOp)) { in collectShuffleElements()
1547 Value *ScalarOp = InsElt.getOperand(1); in foldTruncInsEltPair() local
1580 if (!match(ScalarOp, m_Trunc(m_Value(X))) || in foldTruncInsEltPair()
1585 !match(ScalarOp, m_Trunc(m_LShr(m_Specific(X), m_ConstantInt(ShAmt))))) in foldTruncInsEltPair()
1608 Value *ScalarOp = IE.getOperand(1); in visitInsertElementInst() local
1612 VecOp, ScalarOp, IdxOp, SQ.getWithInstruction(&IE))) in visitInsertElementInst()
[all …]
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| H A D | InstCombineCasts.cpp | 663 Value *ScalarOp = InsElt->getOperand(1); in shrinkInsertElt() local
670 Value *NarrowOp = Builder.CreateCast(Opcode, ScalarOp, DestScalarTy); in shrinkInsertElt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 1223 SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG) const;
1224 SDValue LowerPredReductionToSVE(SDValue ScalarOp, SelectionDAG &DAG) const;
1225 SDValue LowerReductionToSVE(unsigned Opcode, SDValue ScalarOp,
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| H A D | AArch64ISelLowering.cpp | 15160 static SDValue getReductionSDNode(unsigned Op, SDLoc DL, SDValue ScalarOp, in getReductionSDNode() argument
15162 SDValue VecOp = ScalarOp.getOperand(0); in getReductionSDNode()
15164 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ScalarOp.getValueType(), Rdx, in getReductionSDNode()
27641 SDValue AArch64TargetLowering::LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, in LowerVECREDUCE_SEQ_FADD() argument
27643 SDLoc DL(ScalarOp); in LowerVECREDUCE_SEQ_FADD()
27644 SDValue AccOp = ScalarOp.getOperand(0); in LowerVECREDUCE_SEQ_FADD()
27645 SDValue VecOp = ScalarOp.getOperand(1); in LowerVECREDUCE_SEQ_FADD()
27713 SDValue ScalarOp, in LowerReductionToSVE() argument
27715 SDLoc DL(ScalarOp); in LowerReductionToSVE()
27716 SDValue VecOp = ScalarOp.getOperand(0); in LowerReductionToSVE()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | ConstantFold.cpp | 376 Constant *ScalarOp = ConstantExpr::getExtractElement(Op, Idx); in ConstantFoldExtractElementInstruction() local
377 if (!ScalarOp) in ConstantFoldExtractElementInstruction()
379 Ops.push_back(ScalarOp); in ConstantFoldExtractElementInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 1989 SDValue ScalarOp = DAG.getNode(Node->getOpcode(), dl, ValueVTs, Opers); in UnrollStrictFPOp() local
1990 SDValue ScalarResult = ScalarOp.getValue(0); in UnrollStrictFPOp()
1991 SDValue ScalarChain = ScalarOp.getValue(1); in UnrollStrictFPOp()
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| H A D | SelectionDAG.cpp | 6715 SDValue ScalarOp = in FoldConstantArithmetic() local
6717 EVT ScalarVT = ScalarOp.getValueType(); in FoldConstantArithmetic()
6726 if (NewNodesMustHaveLegalTypes && !ScalarOp.isUndef() && in FoldConstantArithmetic()
6727 !isa<ConstantSDNode>(ScalarOp) && in FoldConstantArithmetic()
6731 ScalarOp = getNode(ISD::TRUNCATE, DL, InSVT, ScalarOp); in FoldConstantArithmetic()
6734 ScalarOps.push_back(ScalarOp); in FoldConstantArithmetic()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 6283 for (MachineOperand *ScalarOp : ScalarOps) { in emitLoadScalarOpsFromVGPRLoop()
6284 unsigned RegSize = TRI->getRegSizeInBits(ScalarOp->getReg(), MRI); in emitLoadScalarOpsFromVGPRLoop()
6286 Register VScalarOp = ScalarOp->getReg(); in emitLoadScalarOpsFromVGPRLoop()
6312 ScalarOp->setReg(CurReg); in emitLoadScalarOpsFromVGPRLoop()
6313 ScalarOp->setIsKill(); in emitLoadScalarOpsFromVGPRLoop()
6315 unsigned VScalarOpUndef = getUndefRegState(ScalarOp->isUndef()); in emitLoadScalarOpsFromVGPRLoop()
6378 ScalarOp->setReg(SScalarOp); in emitLoadScalarOpsFromVGPRLoop()
6379 ScalarOp->setIsKill(); in emitLoadScalarOpsFromVGPRLoop()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 8790 SDValue &ScalarOp = Operands[SplatOp]; in lowerVectorIntrinsicScalars()
8791 MVT OpVT = ScalarOp.getSimpleValueType(); in lowerVectorIntrinsicScalars()
8805 isa<ConstantSDNode>(ScalarOp) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND; in lowerVectorIntrinsicScalars()
8806 ScalarOp = DAG.getNode(ExtOpc, DL, XLenVT, ScalarOp); in lowerVectorIntrinsicScalars()
8825 if (DAG.ComputeNumSignBits(ScalarOp) > 32) { in lowerVectorIntrinsicScalars()
8826 ScalarOp = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, ScalarOp); in lowerVectorIntrinsicScalars()
8844 DAG.SplitScalar(ScalarOp, DL, MVT::i32, MVT::i32); in lowerVectorIntrinsicScalars()
8939 ScalarOp in lowerVectorIntrinsicScalars()
8788 SDValue &ScalarOp = Operands[SplatOp]; lowerVectorIntrinsicScalars() local
9028 SDValue &ScalarOp = Operands[SplatOp]; promoteVCIXScalar() local
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