| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineVectorOps.cpp | 659 Value *ScalarOp = IEI->getOperand(1); in collectSingleShuffleElements() local
666 if (isa<PoisonValue>(ScalarOp)) { // inserting poison into vector. in collectSingleShuffleElements()
674 } else if (ExtractElementInst *EI = dyn_cast<ExtractElementInst>(ScalarOp)){ in collectSingleShuffleElements()
813 Value *ScalarOp = IEI->getOperand(1); in collectShuffleElements() local
816 if (ExtractElementInst *EI = dyn_cast<ExtractElementInst>(ScalarOp)) { in collectShuffleElements()
1625 Value *ScalarOp = InsElt.getOperand(1); in foldTruncInsEltPair() local
1658 if (!match(ScalarOp, m_Trunc(m_Value(X))) || in foldTruncInsEltPair()
1663 !match(ScalarOp, m_Trunc(m_LShr(m_Specific(X), m_ConstantInt(ShAmt))))) in foldTruncInsEltPair()
1686 Value *ScalarOp = IE.getOperand(1); in visitInsertElementInst() local
1690 VecOp, ScalarOp, IdxOp, SQ.getWithInstruction(&IE))) in visitInsertElementInst()
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| H A D | InstCombineCasts.cpp | 739 Value *ScalarOp = InsElt->getOperand(1); in shrinkInsertElt() local
746 Value *NarrowOp = Builder.CreateCast(Opcode, ScalarOp, DestScalarTy); in shrinkInsertElt()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 737 SDValue LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, SelectionDAG &DAG) const;
738 SDValue LowerPredReductionToSVE(SDValue ScalarOp, SelectionDAG &DAG) const;
739 SDValue LowerReductionToSVE(unsigned Opcode, SDValue ScalarOp,
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| H A D | AArch64ISelLowering.cpp | 15933 static SDValue getReductionSDNode(unsigned Op, SDLoc DL, SDValue ScalarOp, in getReductionSDNode() argument
15935 SDValue VecOp = ScalarOp.getOperand(0); in getReductionSDNode()
15937 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ScalarOp.getValueType(), Rdx, in getReductionSDNode()
29255 SDValue AArch64TargetLowering::LowerVECREDUCE_SEQ_FADD(SDValue ScalarOp, in LowerVECREDUCE_SEQ_FADD() argument
29257 SDLoc DL(ScalarOp); in LowerVECREDUCE_SEQ_FADD()
29258 SDValue AccOp = ScalarOp.getOperand(0); in LowerVECREDUCE_SEQ_FADD()
29259 SDValue VecOp = ScalarOp.getOperand(1); in LowerVECREDUCE_SEQ_FADD()
29327 SDValue ScalarOp, in LowerReductionToSVE() argument
29329 SDLoc DL(ScalarOp); in LowerReductionToSVE()
29330 SDValue VecOp = ScalarOp.getOperand(0); in LowerReductionToSVE()
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | ConstantFold.cpp | 371 Constant *ScalarOp = ConstantExpr::getExtractElement(Op, Idx); in ConstantFoldExtractElementInstruction() local
372 if (!ScalarOp) in ConstantFoldExtractElementInstruction()
374 Ops.push_back(ScalarOp); in ConstantFoldExtractElementInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorOps.cpp | 2317 SDValue ScalarOp = DAG.getNode(Node->getOpcode(), dl, ValueVTs, Opers); in UnrollStrictFPOp() local
2318 SDValue ScalarResult = ScalarOp.getValue(0); in UnrollStrictFPOp()
2319 SDValue ScalarChain = ScalarOp.getValue(1); in UnrollStrictFPOp()
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| H A D | SelectionDAG.cpp | 7166 SDValue ScalarOp = in FoldConstantArithmetic() local
7168 EVT ScalarVT = ScalarOp.getValueType(); in FoldConstantArithmetic()
7177 if (NewNodesMustHaveLegalTypes && !ScalarOp.isUndef() && in FoldConstantArithmetic()
7178 !isa<ConstantSDNode>(ScalarOp) && in FoldConstantArithmetic()
7182 ScalarOp = getNode(ISD::TRUNCATE, DL, InSVT, ScalarOp); in FoldConstantArithmetic()
7185 ScalarOps.push_back(ScalarOp); in FoldConstantArithmetic()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 6588 for (MachineOperand *ScalarOp : ScalarOps) { in emitLoadScalarOpsFromVGPRLoop()
6589 unsigned RegSize = TRI->getRegSizeInBits(ScalarOp->getReg(), MRI); in emitLoadScalarOpsFromVGPRLoop()
6591 Register VScalarOp = ScalarOp->getReg(); in emitLoadScalarOpsFromVGPRLoop()
6617 ScalarOp->setReg(CurReg); in emitLoadScalarOpsFromVGPRLoop()
6618 ScalarOp->setIsKill(); in emitLoadScalarOpsFromVGPRLoop()
6621 unsigned VScalarOpUndef = getUndefRegState(ScalarOp->isUndef()); in emitLoadScalarOpsFromVGPRLoop()
6686 ScalarOp->setReg(SScalarOp); in emitLoadScalarOpsFromVGPRLoop()
6687 ScalarOp->setIsKill(); in emitLoadScalarOpsFromVGPRLoop()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 10314 SDValue &ScalarOp = Operands[SplatOp]; in lowerVectorIntrinsicScalars() local
10315 MVT OpVT = ScalarOp.getSimpleValueType(); in lowerVectorIntrinsicScalars()
10329 isa<ConstantSDNode>(ScalarOp) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND; in lowerVectorIntrinsicScalars()
10330 ScalarOp = DAG.getNode(ExtOpc, DL, XLenVT, ScalarOp); in lowerVectorIntrinsicScalars()
10349 if (DAG.ComputeNumSignBits(ScalarOp) > 32) { in lowerVectorIntrinsicScalars()
10350 ScalarOp = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, ScalarOp); in lowerVectorIntrinsicScalars()
10368 DAG.SplitScalar(ScalarOp, DL, MVT::i32, MVT::i32); in lowerVectorIntrinsicScalars()
10456 ScalarOp = splatSplitI64WithVL(DL, VT, SDValue(), ScalarOp, VL, DAG); in lowerVectorIntrinsicScalars()
10547 SDValue &ScalarOp = Operands[SplatOp]; in promoteVCIXScalar() local
10548 MVT OpVT = ScalarOp.getSimpleValueType(); in promoteVCIXScalar()
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