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/freebsd/crypto/openssl/crypto/bn/asm/
H A Dppc.pl118 $ST= "stw"; # store
142 $ST= "std"; # store
302 $ST r9,`0*$BNSZ`(r3) # r[0]=c1;
317 $ST r10,`1*$BNSZ`(r3) #r[1]=c2;
336 $ST r11,`2*$BNSZ`(r3) #r[2]=c3
360 $ST r9,`3*$BNSZ`(r3) #r[3]=c1
378 $ST r10,`4*$BNSZ`(r3) #r[4]=c2
390 $ST r11,`5*$BNSZ`(r3) #r[5] = c3
397 $ST r9,`6*$BNSZ`(r3) #r[6]=c1
398 $ST r10,`7*$BNSZ`(r3) #r[7]=c2
[all …]
H A Dppc-mont.pl58 $ST= "stw"; # store
67 $PUSH= $ST;
79 $ST= "std"; # store
88 $PUSH= $ST;
214 $ST $lo1,0($tp) ; tp[j-1]
227 $ST $lo1,0($tp) ; tp[j-1]
232 $ST $hi1,$BNSZ($tp)
278 $ST $lo1,0($tp) ; tp[j-1]
292 $ST $lo1,0($tp) ; tp[j-1]
298 $ST $hi1,$BNSZ($tp)
[all …]
H A Dmips.pl64 $ST="sd";
79 $ST="sw";
188 $ST $t1,0($a0)
201 $ST $t3,$BNSZ($a0)
215 $ST $ta1,-2*$BNSZ($a0)
227 $ST $ta3,-$BNSZ($a0)
248 $ST $t1,0($a0)
263 $ST $t1,$BNSZ($a0)
277 $ST $t1,2*$BNSZ($a0)
340 $ST $v0,0($a0)
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsLegalizerInfo.cpp68 MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { in MipsLegalizerInfo() argument
83 .legalIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
86 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) in MipsLegalizerInfo()
107 .legalIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
110 {s32, p0, 16, ST.systemSupportsUnalignedAccess()}, in MipsLegalizerInfo()
113 {s64, p0, 64, ST.systemSupportsUnalignedAccess()}})) in MipsLegalizerInfo()
115 if (ST.hasMSA() && CheckTy0Ty1MemSizeAlign( in MipsLegalizerInfo()
126 .customIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
141 if (!ST.systemSupportsUnalignedAccess() && in MipsLegalizerInfo()
199 .legalIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVLegalizerInfo.cpp35 const RISCVSubtarget &ST) { in typeIsScalarFPArith() argument
36 return [=, &ST](const LegalityQuery &Query) { in typeIsScalarFPArith()
38 ((ST.hasStdExtZfh() && Query.Types[TypeIdx].getSizeInBits() == 16) || in typeIsScalarFPArith()
39 (ST.hasStdExtF() && Query.Types[TypeIdx].getSizeInBits() == 32) || in typeIsScalarFPArith()
40 (ST.hasStdExtD() && Query.Types[TypeIdx].getSizeInBits() == 64)); in typeIsScalarFPArith()
47 const RISCVSubtarget &ST) { in typeIsLegalIntOrFPVec() argument
48 LegalityPredicate P = [=, &ST](const LegalityQuery &Query) { in typeIsLegalIntOrFPVec()
49 return ST.hasVInstructions() && in typeIsLegalIntOrFPVec()
51 ST.hasVInstructionsI64()) && in typeIsLegalIntOrFPVec()
53 ST.getELen() == 64); in typeIsLegalIntOrFPVec()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVModuleAnalysis.cpp75 unsigned i, const SPIRVSubtarget &ST, in getSymbolicOperandRequirements() argument
82 VersionTuple SPIRVVersion = ST.getSPIRVVersion(); in getSymbolicOperandRequirements()
120 if (llvm::all_of(ReqExts, [&ST](const SPIRV::Extension::Extension &Ext) { in getSymbolicOperandRequirements()
121 return ST.canUseExtension(Ext); in getSymbolicOperandRequirements()
142 MAI.Reqs.initAvailableCapabilities(*ST); in setBaseInfo()
153 MAI.Mem = ST->isOpenCLEnv() ? SPIRV::MemoryModel::OpenCL in setBaseInfo()
156 unsigned PtrSize = ST->getPointerSize(); in setBaseInfo()
184 if (ST->isOpenCLEnv()) { in setBaseInfo()
206 MAI.Mem, *ST); in setBaseInfo()
208 MAI.SrcLang, *ST); in setBaseInfo()
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/freebsd/contrib/file/magic/Magdir/
H A Duf229 >>28 lelong 0x00ff6919 ST STM32L4xx
30 >>28 lelong 0x04240bdf ST STM32L5xx
31 >>28 lelong 0x06d1097b ST STM32F411xC
37 >>28 lelong 0x1e1f432d ST STM32L1xx
38 >>28 lelong 0x202e3a91 ST STM32L0xx
39 >>28 lelong 0x21460ff0 ST STM32WLxx
43 >>28 lelong 0x2dc309c5 ST STM32F411xE
44 >>28 lelong 0x300f5633 ST STM32G0xx
50 >>28 lelong 0x4c71240a ST STM32G4xx
54 >>28 lelong 0x53b80f00 ST STM32F7xx
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.h35 const RISCVSubtarget *ST; variable
38 const RISCVSubtarget *getST() const { return ST; } in getST()
60 : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)), in RISCVTTIImpl()
61 TLI(ST->getTargetLowering()) {} in RISCVTTIImpl()
100 bool supportsScalableVectors() const { return ST->hasVInstructions(); } in supportsScalableVectors()
102 bool enableScalableVectorization() const { return ST->hasVInstructions(); } in enableScalableVectorization()
105 return ST->hasVInstructions() ? TailFoldingStyle::Data in getPreferredTailFoldingStyle()
142 return ST->useRVVForFixedLengthVectors() ? 16 : 0; in getMinVectorRegisterBitWidth()
221 if (!ST->hasVInstructions()) in isLegalMaskedLoadStore()
227 if (DataTypeVT.isFixedLengthVector() && !ST->useRVVForFixedLengthVectors()) in isLegalMaskedLoadStore()
[all …]
H A DRISCVOptWInstrs.cpp69 const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
71 const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
73 const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
120 const RISCVSubtarget &ST, in hasAllNBitUsers() argument
200 if (Bits >= (ST.getXLen() / 2)) in hasAllNBitUsers()
219 if (Bits >= (ST.getXLen() - UserMI->getOperand(2).getImm())) in hasAllNBitUsers()
244 if (Bits >= Log2_32(ST.getXLen())) in hasAllNBitUsers()
256 if (OpIdx == 2 && Bits >= Log2_32(ST.getXLen())) in hasAllNBitUsers()
344 static bool hasAllWUsers(const MachineInstr &OrigMI, const RISCVSubtarget &ST, in hasAllWUsers() argument
346 return hasAllNBitUsers(OrigMI, ST, MRI, 32); in hasAllWUsers()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp108 if (ST->hasMVEIntegerOps()) in getPreferredAddressingMode()
114 if (ST->isMClass() && ST->isThumb2() && in getPreferredAddressingMode()
311 if (!ST->isThumb()) { in getIntImmCost()
316 return ST->hasV6T2Ops() ? 2 : 3; in getIntImmCost()
318 if (ST->isThumb2()) { in getIntImmCost()
323 return ST->hasV6T2Ops() ? 2 : 3; in getIntImmCost()
428 if (ST->isThumb2() && NegImm < 1<<12) in getIntImmCostInst()
431 if (ST->isThumb() && NegImm < 1<<8) in getIntImmCostInst()
442 if (Inst && ((ST->hasV6Ops() && !ST->isThumb()) || ST->isThumb2()) && in getIntImmCostInst()
450 if (Inst && ST->hasVFP2Base() && isFPSatMinMaxPattern(Inst, Imm)) in getIntImmCostInst()
[all …]
H A DARMSLSHardening.cpp38 const ARMSubtarget *ST; member in __anon5439c0b70111::ARMSLSHardening
70 static void insertSpeculationBarrier(const ARMSubtarget *ST, in insertSpeculationBarrier() argument
82 const TargetInstrInfo *TII = ST->getInstrInfo(); in insertSpeculationBarrier()
83 assert(ST->hasDataBarrier() || ST->hasSB()); in insertSpeculationBarrier()
84 bool ProduceSB = ST->hasSB() && !AlwaysUseISBDSB; in insertSpeculationBarrier()
86 ProduceSB ? (ST->isThumb() ? ARM::t2SpeculationBarrierSBEndBB in insertSpeculationBarrier()
88 : (ST->isThumb() ? ARM::t2SpeculationBarrierISBDSBEndBB in insertSpeculationBarrier()
95 ST = &MF.getSubtarget<ARMSubtarget>(); in runOnMachineFunction()
108 if (!ST->hardenSlsRetBr()) in hardenReturnsAndBRs()
110 assert(!ST->isThumb1Only()); in hardenReturnsAndBRs()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCTargetTransformInfo.h33 const ARCSubtarget *ST; variable
36 const ARCSubtarget *getST() const { return ST; } in getST()
41 : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl()), in ARCTTIImpl()
42 TLI(ST->getTargetLowering()) {} in ARCTTIImpl()
46 : BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {} in ARCTTIImpl()
48 : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)), in ARCTTIImpl()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchTargetTransformInfo.cpp27 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); in getRegisterBitWidth()
29 if (ST->hasExtLASX()) in getRegisterBitWidth()
31 if (ST->hasExtLSX()) in getRegisterBitWidth()
47 return ST->hasBasicF() ? 32 : 0; in getNumberOfRegisters()
49 return ST->hasExtLSX() ? 32 : 0; in getNumberOfRegisters()
62 if ((ScalarTy->isFloatTy() && ST->hasBasicF()) || in getRegisterClassForType()
63 (ScalarTy->isDoubleTy() && ST->hasBasicD())) { in getRegisterClassForType()
71 return ST->getMaxInterleaveFactor(); in getMaxInterleaveFactor()
H A DLoongArchOptWInstrs.cpp68 const LoongArchSubtarget &ST,
71 const LoongArchSubtarget &ST,
74 const LoongArchSubtarget &ST,
99 const LoongArchSubtarget &ST, in hasAllNBitUsers() argument
201 if (Bits >= (ST.getGRLen() - UserMI->getOperand(2).getImm())) in hasAllNBitUsers()
223 if (Bits >= Log2_32(ST.getGRLen())) in hasAllNBitUsers()
234 if (OpIdx == 2 && Bits >= Log2_32(ST.getGRLen())) in hasAllNBitUsers()
316 const LoongArchSubtarget &ST, in hasAllWUsers() argument
318 return hasAllNBitUsers(OrigMI, ST, MRI, 32); in hasAllWUsers()
477 static bool isSignExtendedW(Register SrcReg, const LoongArchSubtarget &ST, in isSignExtendedW() argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/DirectX/
H A DCBufferDataLayout.cpp25 StructType *ST; member
43 LegacyStructLayout &getStructLayout(StructType *ST);
73 if (auto *ST = dyn_cast<StructType>(Ty)) { in getTypeAllocSize() local
74 LegacyStructLayout &Layout = getStructLayout(ST); in getTypeAllocSize()
93 LegacyCBufferLayout::getStructLayout(StructType *ST) { in getStructLayout() argument
94 auto it = StructLayouts.find(ST); in getStructLayout()
100 Layout.ST = ST; in getStructLayout()
101 for (Type *EltTy : ST->elements()) { in getStructLayout()
110 StructLayouts[ST] in getStructLayout()
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/freebsd/contrib/llvm-project/llvm/lib/TableGen/
H A DSetTheory.cpp39 void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, in apply()
41 ST.evaluate(Expr->arg_begin(), Expr->arg_end(), Elts, Loc); in apply()
47 void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, in apply()
53 ST.evaluate(*Expr->arg_begin(), Add, Loc); in apply()
54 ST.evaluate(Expr->arg_begin() + 1, Expr->arg_end(), Sub, Loc); in apply()
63 void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, in apply()
69 ST.evaluate(Expr->arg_begin()[0], S1, Loc); in apply()
70 ST.evaluate(Expr->arg_begin()[1], S2, Loc); in apply()
79 virtual void apply2(SetTheory &ST, DagInit *Expr, RecSet &Set, int64_t N,
82 void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, in apply()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.h48 const AArch64Subtarget *ST; variable
51 const AArch64Subtarget *getST() const { return ST; } in getST()
74 : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)), in AArch64TTIImpl()
75 TLI(ST->getTargetLowering()) {} in AArch64TTIImpl()
109 bool enableMaskedInterleavedAccessVectorization() { return ST->hasSVE(); } in enableMaskedInterleavedAccessVectorization()
114 if (ST->hasNEON()) in getNumberOfRegisters()
136 return ST->getMinVectorRegisterBitWidth(); in getMinVectorRegisterBitWidth()
140 return ST->getVScaleForTuning(); in getVScaleForTuning()
155 return VF.getKnownMinValue() * ST->getVScaleForTuning(); in getMaxNumElements()
245 if (Ty->isBFloatTy() && ST->hasBF16()) in isElementTypeLegalForScalableVector()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIProgramInfo.cpp79 const GCNSubtarget &ST) { in getComputePGMRSrc1Reg() argument
87 if (ST.hasDX10ClampMode()) in getComputePGMRSrc1Reg()
90 if (ST.hasIEEEMode()) in getComputePGMRSrc1Reg()
93 if (ST.hasRrWGMode()) in getComputePGMRSrc1Reg()
100 CallingConv::ID CC, const GCNSubtarget &ST) { in getPGMRSrc1Reg() argument
106 if (ST.hasDX10ClampMode()) in getPGMRSrc1Reg()
109 if (ST.hasIEEEMode()) in getPGMRSrc1Reg()
112 if (ST.hasRrWGMode()) in getPGMRSrc1Reg()
164 const MCExpr *SIProgramInfo::getComputePGMRSrc1(const GCNSubtarget &ST, in getComputePGMRSrc1() argument
166 uint64_t Reg = getComputePGMRSrc1Reg(*this, ST); in getComputePGMRSrc1()
[all …]
H A DGCNHazardRecognizer.cpp52 const GCNSubtarget &ST);
58 ST(MF.getSubtarget<GCNSubtarget>()), in GCNHazardRecognizer()
59 TII(*ST.getInstrInfo()), in GCNHazardRecognizer()
64 TSchedModel.init(&ST); in GCNHazardRecognizer()
65 RunLdsBranchVmemWARHazardFixup = shouldRunLdsBranchVmemWARHazardFixup(MF, ST); in GCNHazardRecognizer()
123 static bool isXDL(const GCNSubtarget &ST, const MachineInstr &MI) { in isXDL() argument
132 if (!ST.hasGFX940Insts()) in isXDL()
197 if (ST.hasNSAtoVMEMBug() && checkNSAtoVMEMHazard(MI) > 0) in getHazardType()
203 if (ST.hasNoDataDepHazard()) in getHazardType()
238 if (((ST.hasReadM0MovRelInterpHazard() && in getHazardType()
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H A DSIFrameLowering.cpp79 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in getVGPRSpillLaneOrTempRegister() local
80 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in getVGPRSpillLaneOrTempRegister()
134 static void buildPrologSpill(const GCNSubtarget &ST, const SIRegisterInfo &TRI, in buildPrologSpill() argument
141 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR in buildPrologSpill()
157 static void buildEpilogRestore(const GCNSubtarget &ST, in buildEpilogRestore() argument
165 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR in buildEpilogRestore()
228 const GCNSubtarget &ST; member in llvm::PrologEpilogSGPRSpillBuilder
260 buildPrologSpill(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MI, DL, TmpVGPR, in saveToMemory()
306 buildEpilogRestore(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MI, DL, in restoreFromMemory()
345 ST(MF.getSubtarget<GCNSubtarget>()), MFI(MF.getFrameInfo()), in PrologEpilogSGPRSpillBuilder()
[all …]
H A DSIInsertHardClauses.cpp95 const GCNSubtarget *ST = nullptr; member in __anonefe30cd30111::SIInsertHardClauses
105 if (MI.mayLoad() || (MI.mayStore() && ST->shouldClusterStores())) { in getHardClauseType()
106 if (ST->getGeneration() == AMDGPUSubtarget::GFX10) { in getHardClauseType()
108 if (ST->hasNSAClauseBug()) { in getHardClauseType()
118 assert(ST->getGeneration() >= AMDGPUSubtarget::GFX11); in getHardClauseType()
180 assert(CI.Length <= ST->maxHardClauseLength() && in emitClause()
196 ST = &MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
197 if (!ST->hasHardClauses()) in runOnMachineFunction()
200 const SIInstrInfo *SII = ST->getInstrInfo(); in runOnMachineFunction()
201 const TargetRegisterInfo *TRI = ST->getRegisterInfo(); in runOnMachineFunction()
[all …]
H A DSIMachineFunctionInfo.cpp46 const GCNSubtarget &ST = *static_cast<const GCNSubtarget *>(STI); in SIMachineFunctionInfo() local
47 FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F); in SIMachineFunctionInfo()
48 WavesPerEU = ST.getWavesPerEU(F); in SIMachineFunctionInfo()
49 MaxNumWorkGroups = ST.getMaxNumWorkGroups(F); in SIMachineFunctionInfo()
52 Occupancy = ST.computeOccupancy(F, getLDSSize()); in SIMachineFunctionInfo()
67 MayNeedAGPRs = ST.hasMAIInsts(); in SIMachineFunctionInfo()
89 if (!ST.enableFlatScratch()) { in SIMachineFunctionInfo()
102 MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(), in SIMachineFunctionInfo()
105 if (ST.hasGFX90AInsts() && in SIMachineFunctionInfo()
106 ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() && in SIMachineFunctionInfo()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSectionXCOFF.h46 XCOFF::SymbolType ST, SectionKind K, MCSymbolXCOFF *QualName, in MCSectionXCOFF() argument
50 /*IsVirtual=*/ST == XCOFF::XTY_CM && SMC != XCOFF::XMC_TD, in MCSectionXCOFF()
52 CsectProp(XCOFF::CsectProperties(SMC, ST)), QualName(QualName), in MCSectionXCOFF()
56 (ST == XCOFF::XTY_SD || ST == XCOFF::XTY_CM || ST == XCOFF::XTY_ER) && in MCSectionXCOFF()
60 assert((ST == XCOFF::XTY_CM || ST == XCOFF::XTY_ER) && in MCSectionXCOFF()
65 if (ST != XCOFF::XTY_ER) { in MCSectionXCOFF()
/freebsd/stand/efi/loader/arch/i386/
H A Dsetup.c39 setup(EFI_HANDLE IH, EFI_SYSTEM_TABLE *ST) { in setup() argument
44 ST->ConOut->OutputString(ST->ConOut, (CHAR16 *) in setup()
47 ST->BootServices->Exit(IH, EFI_UNSUPPORTED, 0, NULL); in setup()
50 return (efi_main(IH, ST)); in setup()
/freebsd/crypto/openssl/crypto/rc4/asm/
H A Drc4-parisc.pl74 $ST="stb";
79 $ST="stw";
110 $ST $TX[0],0($ix)
114 $ST $TY,0($iy)
130 $ST $TX[0],0($iy)
132 $ST $TY,0($ix)
242 $ST $XX[0],`-2*$SZ`($key)
243 $ST $YY,`-1*$SZ`($key)
262 $ST %r0,`0*$SZ`($key)
263 $ST %r0,`1*$SZ`($key)
[all …]

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