| /freebsd/crypto/openssl/crypto/bn/asm/ |
| H A D | ppc.pl | 118 $ST= "stw"; # store
142 $ST= "std"; # store
302 $ST r9,`0*$BNSZ`(r3) # r[0]=c1;
317 $ST r10,`1*$BNSZ`(r3) #r[1]=c2;
336 $ST r11,`2*$BNSZ`(r3) #r[2]=c3
360 $ST r9,`3*$BNSZ`(r3) #r[3]=c1
378 $ST r10,`4*$BNSZ`(r3) #r[4]=c2
390 $ST r11,`5*$BNSZ`(r3) #r[5] = c3
397 $ST r9,`6*$BNSZ`(r3) #r[6]=c1
398 $ST r10,`7*$BNSZ`(r3) #r[7]=c2
[all …]
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| H A D | ppc-mont.pl | 58 $ST= "stw"; # store
67 $PUSH= $ST;
79 $ST= "std"; # store
88 $PUSH= $ST;
214 $ST $lo1,0($tp) ; tp[j-1]
227 $ST $lo1,0($tp) ; tp[j-1]
232 $ST $hi1,$BNSZ($tp)
278 $ST $lo1,0($tp) ; tp[j-1]
292 $ST $lo1,0($tp) ; tp[j-1]
298 $ST $hi1,$BNSZ($tp)
[all …]
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| /freebsd/crypto/krb5/src/lib/crypto/ |
| H A D | Makefile.in | 12 STOBJLISTS=krb/OBJS.ST \
13 builtin/OBJS.ST builtin/des/OBJS.ST \
14 builtin/aes/OBJS.ST builtin/camellia/OBJS.ST \
15 builtin/md4/OBJS.ST builtin/md5/OBJS.ST \
16 builtin/sha1/OBJS.ST builtin/sha2/OBJS.ST \
17 builtin/enc_provider/OBJS.ST builtin/hash_provider/OBJS.ST \
18 openssl/OBJS.ST openssl/des/OBJS.ST \
19 openssl/enc_provider/OBJS.ST openssl/hash_provider/OBJS.ST
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVLegalizerInfo.cpp | 38 const RISCVSubtarget &ST) { in typeIsLegalIntOrFPVec() argument
39 LegalityPredicate P = [=, &ST](const LegalityQuery &Query) { in typeIsLegalIntOrFPVec()
40 return ST.hasVInstructions() && in typeIsLegalIntOrFPVec()
42 ST.hasVInstructionsI64()) && in typeIsLegalIntOrFPVec()
44 ST.getELen() == 64); in typeIsLegalIntOrFPVec()
52 const RISCVSubtarget &ST) { in typeIsLegalBoolVec() argument
53 LegalityPredicate P = [=, &ST](const LegalityQuery &Query) { in typeIsLegalBoolVec()
54 return ST.hasVInstructions() && in typeIsLegalBoolVec()
56 ST.getELen() == 64); in typeIsLegalBoolVec()
63 const RISCVSubtarget &ST) { in typeIsLegalPtrVec() argument
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsLegalizerInfo.cpp | 68 MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { in MipsLegalizerInfo() argument
83 .legalIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
86 if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64})) in MipsLegalizerInfo()
107 .legalIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
110 {s32, p0, 16, ST.systemSupportsUnalignedAccess()}, in MipsLegalizerInfo()
113 {s64, p0, 64, ST.systemSupportsUnalignedAccess()}})) in MipsLegalizerInfo()
115 if (ST.hasMSA() && CheckTy0Ty1MemSizeAlign( in MipsLegalizerInfo()
126 .customIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
141 if (!ST.systemSupportsUnalignedAccess() && in MipsLegalizerInfo()
199 .legalIf([=, &ST](const LegalityQuery &Query) { in MipsLegalizerInfo()
[all …]
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| /freebsd/crypto/krb5/src/lib/crypto/builtin/ |
| H A D | Makefile.in | 28 SUBDIROBJLISTS= des/OBJS.ST md4/OBJS.ST \
29 md5/OBJS.ST sha1/OBJS.ST sha2/OBJS.ST \
30 enc_provider/OBJS.ST \
31 hash_provider/OBJS.ST \
32 aes/OBJS.ST \
33 camellia/OBJS.ST
35 STOBJLISTS= $(SUBDIROBJLISTS) OBJS.ST
|
| /freebsd/contrib/file/magic/Magdir/ |
| H A D | uf2 | 29 >>28 lelong 0x00ff6919 ST STM32L4xx
30 >>28 lelong 0x04240bdf ST STM32L5xx
31 >>28 lelong 0x06d1097b ST STM32F411xC
37 >>28 lelong 0x1e1f432d ST STM32L1xx
38 >>28 lelong 0x202e3a91 ST STM32L0xx
39 >>28 lelong 0x21460ff0 ST STM32WLxx
43 >>28 lelong 0x2dc309c5 ST STM32F411xE
44 >>28 lelong 0x300f5633 ST STM32G0xx
50 >>28 lelong 0x4c71240a ST STM32G4xx
54 >>28 lelong 0x53b80f00 ST STM32F7xx
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVModuleAnalysis.cpp | 67 unsigned i, const SPIRVSubtarget &ST, in getSymbolicOperandRequirements() argument
71 if (!ST.isShader()) in getSymbolicOperandRequirements()
78 VersionTuple SPIRVVersion = ST.getSPIRVVersion(); in getSymbolicOperandRequirements()
122 if (llvm::all_of(ReqExts, [&ST](const SPIRV::Extension::Extension &Ext) { in getSymbolicOperandRequirements()
123 return ST.canUseExtension(Ext); in getSymbolicOperandRequirements()
144 MAI.Reqs.initAvailableCapabilities(*ST); in setBaseInfo()
155 MAI.Mem = ST->isShader() ? SPIRV::MemoryModel::GLSL450 in setBaseInfo()
158 unsigned PtrSize = ST->getPointerSize(); in setBaseInfo()
186 if (!ST->isShader()) { in setBaseInfo()
208 MAI.Mem, *ST); in setBaseInfo()
[all …]
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| /freebsd/crypto/krb5/src/lib/crypto/openssl/ |
| H A D | Makefile.in | 27 SUBDIROBJLISTS= des/OBJS.ST md4/OBJS.ST \
28 md5/OBJS.ST sha1/OBJS.ST sha2/OBJS.ST \
29 enc_provider/OBJS.ST \
30 hash_provider/OBJS.ST \
31 aes/OBJS.ST
33 STOBJLISTS= $(SUBDIROBJLISTS) OBJS.ST
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchTargetTransformInfo.cpp | 27 return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); in getRegisterBitWidth()
29 if (ST->hasExtLASX()) in getRegisterBitWidth()
31 if (ST->hasExtLSX()) in getRegisterBitWidth()
47 return ST->hasBasicF() ? 32 : 0; in getNumberOfRegisters()
49 return ST->hasExtLSX() ? 32 : 0; in getNumberOfRegisters()
62 if ((ScalarTy->isFloatTy() && ST->hasBasicF()) || in getRegisterClassForType()
63 (ScalarTy->isDoubleTy() && ST->hasBasicD())) { in getRegisterClassForType()
71 return ST->getMaxInterleaveFactor(); in getMaxInterleaveFactor()
89 return ST->hasExtLSX() ? TTI::PSK_FastHardware : TTI::PSK_Software; in getPopcntSupport()
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| H A D | LoongArchOptWInstrs.cpp | 68 const LoongArchSubtarget &ST,
71 const LoongArchSubtarget &ST,
74 const LoongArchSubtarget &ST,
99 const LoongArchSubtarget &ST, in hasAllNBitUsers() argument
177 if (Bits >= 32 && ST.hasDiv32()) in hasAllNBitUsers()
231 if (Bits >= (ST.getGRLen() - UserMI->getOperand(2).getImm())) in hasAllNBitUsers()
253 if (Bits >= Log2_32(ST.getGRLen())) in hasAllNBitUsers()
264 if (OpIdx == 2 && Bits >= Log2_32(ST.getGRLen())) in hasAllNBitUsers()
346 const LoongArchSubtarget &ST, in hasAllWUsers() argument
348 return hasAllNBitUsers(OrigMI, ST, MRI, 32); in hasAllWUsers()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCTargetTransformInfo.h | 33 const ARCSubtarget *ST; variable
36 const ARCSubtarget *getST() const { return ST; } in getST()
41 : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl()), in ARCTTIImpl()
42 TLI(ST->getTargetLowering()) {} in ARCTTIImpl()
46 : BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {} in ARCTTIImpl()
48 : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)), in ARCTTIImpl()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SuppressAPXForReloc.cpp | 67 const X86Subtarget &ST, unsigned int OpNum) { in suppressEGPRRegClass() argument
74 const X86RegisterInfo *RI = ST.getRegisterInfo(); in suppressEGPRRegClass()
88 const X86Subtarget &ST, in suppressEGPRRegClassInRegAndUses() argument
90 suppressEGPRRegClass(MRI, MI, ST, OpNum); in suppressEGPRRegClassInRegAndUses()
94 suppressEGPRRegClass(MRI, Use, ST, 0); in suppressEGPRRegClassInRegAndUses()
98 const X86Subtarget &ST) { in handleInstructionWithEGPR() argument
99 if (!ST.hasEGPR()) in handleInstructionWithEGPR()
113 suppressEGPRRegClassInRegAndUses(MRI, MI, ST, OpNo); in handleInstructionWithEGPR()
162 const X86Subtarget &ST) { in handleNDDOrNFInstructions() argument
163 if (!ST.hasNDD() && !ST.hasNF()) in handleNDDOrNFInstructions()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/DirectX/ |
| H A D | CBufferDataLayout.cpp | 25 StructType *ST; member
43 LegacyStructLayout &getStructLayout(StructType *ST);
73 if (auto *ST = dyn_cast<StructType>(Ty)) { in getTypeAllocSize() local
74 LegacyStructLayout &Layout = getStructLayout(ST); in getTypeAllocSize()
93 LegacyCBufferLayout::getStructLayout(StructType *ST) { in getStructLayout() argument
94 auto it = StructLayouts.find(ST); in getStructLayout()
100 Layout.ST = ST; in getStructLayout()
101 for (Type *EltTy : ST->elements()) { in getStructLayout()
110 StructLayouts[ST] in getStructLayout()
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 111 if (ST->hasMVEIntegerOps()) in getPreferredAddressingMode()
117 if (ST->isMClass() && ST->isThumb2() && in getPreferredAddressingMode()
330 if (!ST->isThumb()) { in getIntImmCost()
335 return ST->hasV6T2Ops() ? 2 : 3; in getIntImmCost()
337 if (ST->isThumb2()) { in getIntImmCost()
342 return ST->hasV6T2Ops() ? 2 : 3; in getIntImmCost()
448 if (ST->isThumb2() && NegImm < 1<<12) in getIntImmCostInst()
451 if (ST->isThumb() && NegImm < 1<<8) in getIntImmCostInst()
462 if (Inst && ((ST->hasV6Ops() && !ST->isThumb()) || ST->isThumb2()) && in getIntImmCostInst()
470 if (Inst && ST->hasVFP2Base() && isFPSatMinMaxPattern(Inst, Imm)) in getIntImmCostInst()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/TableGen/ |
| H A D | SetTheory.cpp | 40 void apply(SetTheory &ST, const DagInit *Expr, RecSet &Elts, in apply()
42 ST.evaluate(Expr->arg_begin(), Expr->arg_end(), Elts, Loc); in apply()
48 void apply(SetTheory &ST, const DagInit *Expr, RecSet &Elts, in apply()
54 ST.evaluate(*Expr->arg_begin(), Add, Loc); in apply()
55 ST.evaluate(Expr->arg_begin() + 1, Expr->arg_end(), Sub, Loc); in apply()
64 void apply(SetTheory &ST, const DagInit *Expr, RecSet &Elts, in apply()
70 ST.evaluate(Expr->arg_begin()[0], S1, Loc); in apply()
71 ST.evaluate(Expr->arg_begin()[1], S2, Loc); in apply()
80 virtual void apply2(SetTheory &ST, const DagInit *Expr, RecSet &Set,
83 void apply(SetTheory &ST, const DagInit *Expr, RecSet &Elts, in apply()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNHazardRecognizer.cpp | 57 const GCNSubtarget &ST);
61 ST(MF.getSubtarget<GCNSubtarget>()), TII(*ST.getInstrInfo()), in GCNHazardRecognizer()
65 RunLdsBranchVmemWARHazardFixup = shouldRunLdsBranchVmemWARHazardFixup(MF, ST); in GCNHazardRecognizer()
182 if (ST.hasNSAtoVMEMBug() && checkNSAtoVMEMHazard(MI) > 0) in getHazardType()
188 if (ST.hasNoDataDepHazard()) in getHazardType()
220 if (((ST.hasReadM0MovRelInterpHazard() && in getHazardType()
224 (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI)) || in getHazardType()
225 (ST.hasReadM0LdsDmaHazard() && isLdsDma(*MI)) || in getHazardType()
226 (ST.hasReadM0LdsDirectHazard() && in getHazardType()
320 if (ST.hasNSAtoVMEMBug()) in PreEmitNoopsCommon()
[all …]
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| H A D | SIFrameLowering.cpp | 79 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); in getVGPRSpillLaneOrTempRegister() local
80 const SIRegisterInfo *TRI = ST.getRegisterInfo(); in getVGPRSpillLaneOrTempRegister()
134 static void buildPrologSpill(const GCNSubtarget &ST, const SIRegisterInfo &TRI, in buildPrologSpill() argument
141 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR in buildPrologSpill()
157 static void buildEpilogRestore(const GCNSubtarget &ST, in buildEpilogRestore() argument
165 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR in buildEpilogRestore()
228 const GCNSubtarget &ST; member in llvm::PrologEpilogSGPRSpillBuilder
260 buildPrologSpill(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MI, DL, TmpVGPR, in saveToMemory()
306 buildEpilogRestore(ST, TRI, *FuncInfo, LiveUnits, MF, MBB, MI, DL, in restoreFromMemory()
346 ST(MF.getSubtarget<GCNSubtarget>()), MFI(MF.getFrameInfo()), in PrologEpilogSGPRSpillBuilder()
[all …]
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| H A D | SIProgramInfo.cpp | 82 const GCNSubtarget &ST) { in getComputePGMRSrc1Reg() argument
90 if (ST.hasDX10ClampMode()) in getComputePGMRSrc1Reg()
93 if (ST.hasIEEEMode()) in getComputePGMRSrc1Reg()
97 if (ST.getTargetTriple().getOS() == Triple::OSType::AMDHSA) in getComputePGMRSrc1Reg()
100 if (ST.hasRrWGMode()) in getComputePGMRSrc1Reg()
107 CallingConv::ID CC, const GCNSubtarget &ST) { in getPGMRSrc1Reg() argument
113 if (ST.hasDX10ClampMode()) in getPGMRSrc1Reg()
116 if (ST.hasIEEEMode()) in getPGMRSrc1Reg()
119 if (ST.hasRrWGMode()) in getPGMRSrc1Reg()
171 const MCExpr *SIProgramInfo::getComputePGMRSrc1(const GCNSubtarget &ST, in getComputePGMRSrc1() argument
[all …]
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| H A D | SIMachineFunctionInfo.cpp | 45 const GCNSubtarget &ST = *static_cast<const GCNSubtarget *>(STI); in SIMachineFunctionInfo() local
46 FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F); in SIMachineFunctionInfo()
47 WavesPerEU = ST.getWavesPerEU(F); in SIMachineFunctionInfo()
48 MaxNumWorkGroups = ST.getMaxNumWorkGroups(F); in SIMachineFunctionInfo()
54 if (DynamicVGPRBlockSize == 0 && ST.isDynamicVGPREnabled()) in SIMachineFunctionInfo()
55 DynamicVGPRBlockSize = ST.getDynamicVGPRBlockSize(); in SIMachineFunctionInfo()
57 Occupancy = ST.computeOccupancy(F, getLDSSize()).second; in SIMachineFunctionInfo()
72 MayNeedAGPRs = ST.hasMAIInsts(); in SIMachineFunctionInfo()
73 if (ST.hasGFX90AInsts() && in SIMachineFunctionInfo()
74 ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() && in SIMachineFunctionInfo()
[all …]
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| H A D | GCNVOPDUtils.cpp | 43 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>(); in checkVOPDRegConstraints() local
45 if (IsVOPD3 && !ST.hasVOPD3()) in checkVOPDRegConstraints()
52 const SIRegisterInfo *TRI = dyn_cast<SIRegisterInfo>(ST.getRegisterInfo()); in checkVOPDRegConstraints()
155 bool SkipSrc = ST.getGeneration() >= AMDGPUSubtarget::GFX12 && in checkVOPDRegConstraints()
158 bool AllowSameVGPR = ST.hasGFX1250Insts(); in checkVOPDRegConstraints()
193 const GCNSubtarget &ST = STII.getSubtarget(); in shouldScheduleVOPDAdjacent() local
194 unsigned EncodingFamily = AMDGPU::getVOPDEncodingFamily(ST); in shouldScheduleVOPDAdjacent()
214 return checkVOPD(false) || (ST.hasVOPD3() && checkVOPD(true)); in shouldScheduleVOPDAdjacent()
231 const GCNSubtarget &ST = DAG->MF.getSubtarget<GCNSubtarget>(); in apply() local
232 if (!AMDGPU::hasVOPD(ST) || !ST.isWave32()) { in apply()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.h | 34 const RISCVSubtarget *ST; variable
37 const RISCVSubtarget *getST() const { return ST; } in getST()
73 : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)), in RISCVTTIImpl()
74 TLI(ST->getTargetLowering()) {} in RISCVTTIImpl()
111 return ST->hasVInstructions(); in supportsScalableVectors()
115 return ST->hasVInstructions(); in enableScalableVectorization()
119 return ST->hasVInstructions() ? TailFoldingStyle::Data in getPreferredTailFoldingStyle()
159 return ST->useRVVForFixedLengthVectors() ? 16 : 0; in getMinVectorRegisterBitWidth()
255 if (!ST->hasVInstructions()) in isLegalMaskedLoadStore()
261 if (DataTypeVT.isFixedLengthVector() && !ST->useRVVForFixedLengthVectors()) in isLegalMaskedLoadStore()
[all …]
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| H A D | RISCVOptWInstrs.cpp | 69 const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
71 const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
73 const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
120 const RISCVSubtarget &ST, in hasAllNBitUsers() argument
206 if (Bits >= (ST.getXLen() / 2)) in hasAllNBitUsers()
226 if (Bits >= (ST.getXLen() - ShAmt)) in hasAllNBitUsers()
260 if (Bits >= Log2_32(ST.getXLen())) in hasAllNBitUsers()
272 if (OpIdx == 2 && Bits >= Log2_32(ST.getXLen())) in hasAllNBitUsers()
365 static bool hasAllWUsers(const MachineInstr &OrigMI, const RISCVSubtarget &ST, in hasAllWUsers() argument
367 return hasAllNBitUsers(OrigMI, ST, MRI, 32); in hasAllWUsers()
[all …]
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCSectionXCOFF.h | 46 XCOFF::SymbolType ST, SectionKind K, MCSymbolXCOFF *QualName, in MCSectionXCOFF() argument
50 /*IsVirtual=*/ST == XCOFF::XTY_CM && SMC != XCOFF::XMC_TD, in MCSectionXCOFF()
52 CsectProp(XCOFF::CsectProperties(SMC, ST)), QualName(QualName), in MCSectionXCOFF()
56 (ST == XCOFF::XTY_SD || ST == XCOFF::XTY_CM || ST == XCOFF::XTY_ER) && in MCSectionXCOFF()
60 assert((ST == XCOFF::XTY_CM || ST == XCOFF::XTY_ER) && in MCSectionXCOFF()
65 if (ST != XCOFF::XTY_ER) { in MCSectionXCOFF()
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| /freebsd/stand/efi/loader/arch/i386/ |
| H A D | setup.c | 39 setup(EFI_HANDLE IH, EFI_SYSTEM_TABLE *ST) { in setup() argument
44 ST->ConOut->OutputString(ST->ConOut, (CHAR16 *) in setup()
47 ST->BootServices->Exit(IH, EFI_UNSUPPORTED, 0, NULL); in setup()
50 return (efi_main(IH, ST)); in setup()
|